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365 lines
8.4 KiB
C
365 lines
8.4 KiB
C
/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright 2004 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Change log:
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*
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* 20050101: Eran Liberty (liberty@freescale.com)
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* Initial file creating (porting from 85XX & 8260)
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ----------------------------------------------------------------- */
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typedef enum {
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_unk,
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_off,
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_byp,
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_x8,
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_x4,
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_x2,
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_x1,
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_1x,
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_1_5x,
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_2x,
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_2_5x,
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_3x
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} mult_t;
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typedef struct {
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mult_t core_csb_ratio;
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mult_t vco_divider;
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} corecnf_t;
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corecnf_t corecnf_tab[] = {
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{ _byp, _byp}, /* 0x00 */
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{ _byp, _byp}, /* 0x01 */
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{ _byp, _byp}, /* 0x02 */
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{ _byp, _byp}, /* 0x03 */
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{ _byp, _byp}, /* 0x04 */
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{ _byp, _byp}, /* 0x05 */
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{ _byp, _byp}, /* 0x06 */
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{ _byp, _byp}, /* 0x07 */
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{ _1x, _x2}, /* 0x08 */
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{ _1x, _x4}, /* 0x09 */
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{ _1x, _x8}, /* 0x0A */
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{ _1x, _x8}, /* 0x0B */
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{_1_5x, _x2}, /* 0x0C */
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{_1_5x, _x4}, /* 0x0D */
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{_1_5x, _x8}, /* 0x0E */
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{_1_5x, _x8}, /* 0x0F */
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{ _2x, _x2}, /* 0x10 */
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{ _2x, _x4}, /* 0x11 */
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{ _2x, _x8}, /* 0x12 */
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{ _2x, _x8}, /* 0x13 */
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{_2_5x, _x2}, /* 0x14 */
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{_2_5x, _x4}, /* 0x15 */
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{_2_5x, _x8}, /* 0x16 */
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{_2_5x, _x8}, /* 0x17 */
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{ _3x, _x2}, /* 0x18 */
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{ _3x, _x4}, /* 0x19 */
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{ _3x, _x8}, /* 0x1A */
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{ _3x, _x8}, /* 0x1B */
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};
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/* ----------------------------------------------------------------- */
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/*
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*
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*/
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int get_clocks (void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
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u32 pci_sync_in;
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u8 spmf;
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u8 clkin_div;
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u32 sccr;
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u32 corecnf_tab_index;
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u8 corepll;
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u32 lcrr;
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u32 csb_clk;
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u32 tsec1_clk;
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u32 tsec2_clk;
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u32 core_clk;
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u32 usbmph_clk;
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u32 usbdr_clk;
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u32 i2c_clk;
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u32 enc_clk;
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u32 lbiu_clk;
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u32 lclk_clk;
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u32 ddr_clk;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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#ifndef CFG_HRCW_HIGH
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# error "CFG_HRCW_HIGH must be defined in board config file"
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#endif /* CFG_HCWD_HIGH */
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#if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
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# ifndef CONFIG_83XX_CLKIN
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# error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
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# endif /* CONFIG_83XX_CLKIN */
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# ifdef CONFIG_83XX_PCICLK
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# warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
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# endif /* CONFIG_83XX_PCICLK */
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/* PCI Host Mode */
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if (!(im->reset.rcwh & RCWH_PCIHOST)) {
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/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
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* the im->reset.rcwhr PCI Host Mode is disabled
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* FIXME: findout if there is a way to issue some warning */
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return -2;
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}
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if (im->clk.spmr & SPMR_CKID) {
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/* PCI Clock is half CONFIG_83XX_CLKIN */
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pci_sync_in = CONFIG_83XX_CLKIN / 2;
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}
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else {
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pci_sync_in = CONFIG_83XX_CLKIN;
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}
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#else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
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# ifdef CONFIG_83XX_CLKIN
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# warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
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# endif /* CONFIG_83XX_CLKIN */
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# ifndef CONFIG_83XX_PCICLK
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# error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
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# endif /* CONFIG_83XX_PCICLK */
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/* PCI Agent Mode */
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if (im->reset.rcwh & RCWH_PCIHOST) {
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/* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
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* the im->reset.rcwhr PCI Host Mode is enabled */
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return -3;
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}
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pci_sync_in = CONFIG_83XX_PCICLK;
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#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
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/* we have up to date pci_sync_in */
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spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
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clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
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if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
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csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2;
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}
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else {
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csb_clk = pci_sync_in * spmf * (1 + clkin_div);
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}
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sccr = im->clk.sccr;
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switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
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case 0:
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tsec1_clk = 0;
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break;
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case 1:
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tsec1_clk = csb_clk;
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break;
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case 2:
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tsec1_clk = csb_clk / 2;
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break;
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case 3:
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tsec1_clk = csb_clk / 3;
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break;
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default:
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/* unkown SCCR_TSEC1CM value */
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return -4;
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}
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switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
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case 0:
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tsec2_clk = 0;
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break;
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case 1:
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tsec2_clk = csb_clk;
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break;
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case 2:
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tsec2_clk = csb_clk / 2;
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break;
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case 3:
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tsec2_clk = csb_clk / 3;
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break;
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default:
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/* unkown SCCR_TSEC2CM value */
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return -5;
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}
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i2c_clk = tsec2_clk;
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switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
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case 0:
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enc_clk = 0;
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break;
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case 1:
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enc_clk = csb_clk;
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break;
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case 2:
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enc_clk = csb_clk / 2;
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break;
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case 3:
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enc_clk = csb_clk / 3;
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break;
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default:
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/* unkown SCCR_ENCCM value */
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return -6;
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}
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switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
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case 0:
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usbmph_clk = 0;
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break;
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case 1:
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usbmph_clk = csb_clk;
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break;
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case 2:
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usbmph_clk = csb_clk / 2;
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break;
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case 3:
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usbmph_clk = csb_clk / 3;
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break;
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default:
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/* unkown SCCR_USBMPHCM value */
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return -7;
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}
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switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
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case 0:
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usbdr_clk = 0;
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break;
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case 1:
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usbdr_clk = csb_clk;
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break;
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case 2:
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usbdr_clk = csb_clk / 2;
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break;
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case 3:
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usbdr_clk = csb_clk / 3;
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break;
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default:
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/* unkown SCCR_USBDRCM value */
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return -8;
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}
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if (usbmph_clk != 0
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&& usbdr_clk != 0
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&& usbmph_clk != usbdr_clk ) {
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/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
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return -9;
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}
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lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
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lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
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switch (lcrr) {
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case 2:
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case 4:
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case 8:
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lclk_clk = lbiu_clk / lcrr;
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break;
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default:
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/* unknown lcrr */
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return -10;
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}
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ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
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corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
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corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
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if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
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/* corecnf_tab_index is too high, possibly worng value */
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return -11;
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}
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switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
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case _byp:
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case _x1:
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case _1x:
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core_clk = csb_clk;
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break;
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case _1_5x:
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core_clk = (3 * csb_clk) / 2;
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break;
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case _2x:
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core_clk = 2 * csb_clk;
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break;
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case _2_5x:
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core_clk = ( 5 * csb_clk) / 2;
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break;
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case _3x:
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core_clk = 3 * csb_clk;
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break;
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default:
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/* unkown core to csb ratio */
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return -12;
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}
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gd->csb_clk = csb_clk ;
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gd->tsec1_clk = tsec1_clk ;
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gd->tsec2_clk = tsec2_clk ;
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gd->core_clk = core_clk ;
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gd->usbmph_clk = usbmph_clk;
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gd->usbdr_clk = usbdr_clk ;
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gd->i2c_clk = i2c_clk ;
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gd->enc_clk = enc_clk ;
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gd->lbiu_clk = lbiu_clk ;
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gd->lclk_clk = lclk_clk ;
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gd->ddr_clk = ddr_clk ;
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gd->pci_clk = pci_sync_in;
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gd->cpu_clk = gd->core_clk;
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gd->bus_clk = gd->lbiu_clk;
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return 0;
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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*********************************************/
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ulong get_bus_freq (ulong dummy)
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{
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return gd->csb_clk;
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}
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int print_clock_conf (void)
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{
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printf("Clock configuration:\n");
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printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
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printf(" Core: %4d MHz\n",gd->core_clk/1000000);
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debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
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printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
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debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
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debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
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debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
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debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
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debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
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debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
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return 0;
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}
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