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9efcb10a09
AST2700 SoCs integrates a Ibex 32-bits RISC-V core as the boot MCU for the first stage bootloader execution, namely SPL. This patch implements the preliminary base to successfully run SPL on this RV32-based MCU to the console banner message. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
41 lines
447 B
Plaintext
41 lines
447 B
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/ {
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cpus {
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bootph-all;
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};
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memory@80000000 {
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bootph-all;
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};
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soc0: soc@12000000 {
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bootph-all;
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sdrammc: sdrammc@12c00000 {
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bootph-all;
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};
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syscon0: syscon@12c02000 {
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bootph-all;
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};
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};
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soc1: soc@14000000 {
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bootph-all;
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syscon1: syscon@14c02000 {
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bootph-all;
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};
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uart12: serial@14c33b00 {
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bootph-all;
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};
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ast_ibex_timer: timer {
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bootph-all;
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};
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};
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};
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