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This patch adds watchdog support for the Mediatek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
143 lines
2.9 KiB
C
143 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*
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* Watchdog timer for MT7620 and earlier SoCs
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*/
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#include <div64.h>
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#include <dm.h>
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#include <reset.h>
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#include <wdt.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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struct mt7620_wdt {
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void __iomem *regs;
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u64 timeout;
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};
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#define TIMER_FREQ 40000000
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#define TIMER_MASK 0xffff
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#define TIMER_PRESCALE 65536
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#define TIMER_LOAD 0x00
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#define TIMER_CTL 0x08
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#define TIMER_ENABLE BIT(7)
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#define TIMER_MODE_SHIFT 4
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#define TIMER_MODE_WDT 3
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#define TIMER_PRESCALE_SHIFT 0
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#define TIMER_PRESCALE_65536 15
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static void mt7620_wdt_ping(struct mt7620_wdt *priv)
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{
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u64 val;
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val = (TIMER_FREQ / TIMER_PRESCALE) * priv->timeout;
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do_div(val, 1000);
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if (val > TIMER_MASK)
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val = TIMER_MASK;
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writel(val, priv->regs + TIMER_LOAD);
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}
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static int mt7620_wdt_start(struct udevice *dev, u64 ms, ulong flags)
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{
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struct mt7620_wdt *priv = dev_get_priv(dev);
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priv->timeout = ms;
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mt7620_wdt_ping(priv);
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writel(TIMER_ENABLE | (TIMER_MODE_WDT << TIMER_MODE_SHIFT) |
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(TIMER_PRESCALE_65536 << TIMER_PRESCALE_SHIFT),
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priv->regs + TIMER_CTL);
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return 0;
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}
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static int mt7620_wdt_stop(struct udevice *dev)
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{
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struct mt7620_wdt *priv = dev_get_priv(dev);
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mt7620_wdt_ping(priv);
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clrbits_32(priv->regs + TIMER_CTL, TIMER_ENABLE);
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return 0;
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}
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static int mt7620_wdt_reset(struct udevice *dev)
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{
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struct mt7620_wdt *priv = dev_get_priv(dev);
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mt7620_wdt_ping(priv);
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return 0;
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}
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static int mt7620_wdt_expire_now(struct udevice *dev, ulong flags)
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{
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struct mt7620_wdt *priv = dev_get_priv(dev);
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mt7620_wdt_start(dev, 1, flags);
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/*
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* 0 will disable the timer directly, a positive number must be used
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* instead. Since the timer is a countdown timer, 1 (tick) is used.
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*
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* For a timer with input clock = 40MHz, 1 timer tick is short
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* enough to trigger a timeout immediately.
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*
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* Restore prescale to 1, and load timer with 1 to trigger timeout.
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*/
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writel(TIMER_ENABLE | (TIMER_MODE_WDT << TIMER_MODE_SHIFT),
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priv->regs + TIMER_CTL);
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writel(1, priv->regs + TIMER_LOAD);
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return 0;
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}
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static int mt7620_wdt_probe(struct udevice *dev)
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{
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struct mt7620_wdt *priv = dev_get_priv(dev);
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struct reset_ctl reset_wdt;
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int ret;
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ret = reset_get_by_index(dev, 0, &reset_wdt);
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if (!ret)
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reset_deassert(&reset_wdt);
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priv->regs = dev_remap_addr(dev);
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if (!priv->regs)
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return -EINVAL;
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mt7620_wdt_stop(dev);
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return 0;
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}
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static const struct wdt_ops mt7620_wdt_ops = {
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.start = mt7620_wdt_start,
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.reset = mt7620_wdt_reset,
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.stop = mt7620_wdt_stop,
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.expire_now = mt7620_wdt_expire_now,
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};
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static const struct udevice_id mt7620_wdt_ids[] = {
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{ .compatible = "mediatek,mt7620-wdt" },
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{}
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};
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U_BOOT_DRIVER(mt7620_wdt) = {
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.name = "mt7620_wdt",
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.id = UCLASS_WDT,
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.of_match = mt7620_wdt_ids,
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.probe = mt7620_wdt_probe,
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.priv_auto = sizeof(struct mt7620_wdt),
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.ops = &mt7620_wdt_ops,
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};
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