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https://github.com/smaeul/u-boot.git
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80999a5277
Booting SPEAr600 eval board doesn't work with current mainline U-Boot. With this patch the low-vector bit is left to '0'. Resulting in the common relocation of the vectors to 0 (SDRAM) to work correctly. Tested on the SPEAr600 EVB. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
175 lines
2.7 KiB
ArmAsm
175 lines
2.7 KiB
ArmAsm
/*
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* (C) Copyright 2006
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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/*
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* platform specific initializations are already done in Xloader
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* Initializations already done include
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* DDR, PLLs, IP's clock enable and reset release etc
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*/
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.globl lowlevel_init
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lowlevel_init:
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mov pc, lr
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/* void setfreq(unsigned int device, unsigned int frequency) */
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.global setfreq
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setfreq:
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stmfd sp!,{r14}
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stmfd sp!,{r0-r12}
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mov r8,sp
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ldr sp,SRAM_STACK_V
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/* Saving the function arguements for later use */
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mov r4,r0
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mov r5,r1
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/* Putting DDR into self refresh */
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ldr r0,DDR_07_V
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ldr r1,[r0]
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ldr r2,DDR_ACTIVE_V
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bic r1, r1, r2
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str r1,[r0]
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ldr r0,DDR_57_V
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ldr r1,[r0]
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ldr r2,CYCLES_MASK_V
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bic r1, r1, r2
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ldr r2,REFRESH_CYCLES_V
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orr r1, r1, r2, lsl #16
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str r1,[r0]
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ldr r0,DDR_07_V
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ldr r1,[r0]
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ldr r2,SREFRESH_MASK_V
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orr r1, r1, r2
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str r1,[r0]
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/* flush pipeline */
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b flush
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.align 5
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flush:
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/* Delay to ensure self refresh mode */
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ldr r0,SREFRESH_DELAY_V
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delay:
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sub r0,r0,#1
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cmp r0,#0
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bne delay
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/* Putting system in slow mode */
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ldr r0,SCCTRL_V
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mov r1,#2
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str r1,[r0]
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/* Changing PLL(1/2) frequency */
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mov r0,r4
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mov r1,r5
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cmp r4,#0
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beq pll1_freq
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/* Change PLL2 (DDR frequency) */
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ldr r6,PLL2_FREQ_V
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ldr r7,PLL2_CNTL_V
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b pll2_freq
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pll1_freq:
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/* Change PLL1 (CPU frequency) */
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ldr r6,PLL1_FREQ_V
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ldr r7,PLL1_CNTL_V
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pll2_freq:
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mov r0,r6
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ldr r1,[r0]
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ldr r2,PLLFREQ_MASK_V
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bic r1,r1,r2
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mov r2,r5,lsr#1
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orr r1,r1,r2,lsl#24
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str r1,[r0]
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mov r0,r7
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ldr r1,P1C0A_V
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str r1,[r0]
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ldr r1,P1C0E_V
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str r1,[r0]
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ldr r1,P1C06_V
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str r1,[r0]
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ldr r1,P1C0E_V
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str r1,[r0]
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lock:
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ldr r1,[r0]
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and r1,r1,#1
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cmp r1,#0
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beq lock
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/* Putting system back to normal mode */
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ldr r0,SCCTRL_V
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mov r1,#4
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str r1,[r0]
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/* Putting DDR back to normal */
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ldr r0,DDR_07_V
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ldr r1,[R0]
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ldr r2,SREFRESH_MASK_V
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bic r1, r1, r2
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str r1,[r0]
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ldr r2,DDR_ACTIVE_V
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orr r1, r1, r2
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str r1,[r0]
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/* Delay to ensure self refresh mode */
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ldr r0,SREFRESH_DELAY_V
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1:
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sub r0,r0,#1
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cmp r0,#0
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bne 1b
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mov sp,r8
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/* Resuming back to code */
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ldmia sp!,{r0-r12}
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ldmia sp!,{pc}
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SCCTRL_V:
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.word 0xfca00000
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PLL1_FREQ_V:
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.word 0xfca8000C
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PLL1_CNTL_V:
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.word 0xfca80008
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PLL2_FREQ_V:
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.word 0xfca80018
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PLL2_CNTL_V:
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.word 0xfca80014
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PLLFREQ_MASK_V:
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.word 0xff000000
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P1C0A_V:
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.word 0x1C0A
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P1C0E_V:
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.word 0x1C0E
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P1C06_V:
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.word 0x1C06
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SREFRESH_DELAY_V:
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.word 0x9999
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SRAM_STACK_V:
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.word 0xD2800600
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DDR_07_V:
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.word 0xfc60001c
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DDR_ACTIVE_V:
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.word 0x01000000
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DDR_57_V:
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.word 0xfc6000e4
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CYCLES_MASK_V:
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.word 0xffff0000
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REFRESH_CYCLES_V:
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.word 0xf0f0
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SREFRESH_MASK_V:
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.word 0x00010000
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.global setfreq_sz
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setfreq_sz:
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.word setfreq_sz - setfreq
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