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https://github.com/smaeul/u-boot.git
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3d2d115a30
Add minimal devicetree for STM32MP157C-ED1 board, with only the devices to allow boot from SDCARD: - RCC for clock and reset - UART4 for console - I2C and PMIC - DDR - SDMMC0 for SDCard Waiting Kernel upstream for alignment. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
244 lines
4.2 KiB
C
244 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
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/*
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* Copyright (C) STMicroelectronics 2017 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
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*/
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/* OSCILLATOR clocks */
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#define CK_HSE 0
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#define CK_CSI 1
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#define CK_LSI 2
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#define CK_LSE 3
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#define CK_HSI 4
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#define CK_HSE_DIV2 5
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/* Bus clocks */
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#define TIM2 6
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#define TIM3 7
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#define TIM4 8
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#define TIM5 9
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#define TIM6 10
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#define TIM7 11
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#define TIM12 12
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#define TIM13 13
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#define TIM14 14
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#define LPTIM1 15
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#define SPI2 16
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#define SPI3 17
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#define USART2 18
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#define USART3 19
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#define UART4 20
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#define UART5 21
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#define UART7 22
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#define UART8 23
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#define I2C1 24
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#define I2C2 25
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#define I2C3 26
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#define I2C5 27
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#define SPDIF 28
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#define CEC 29
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#define DAC12 30
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#define MDIO 31
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#define TIM1 32
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#define TIM8 33
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#define TIM15 34
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#define TIM16 35
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#define TIM17 36
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#define SPI1 37
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#define SPI4 38
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#define SPI5 39
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#define USART6 40
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#define SAI1 41
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#define SAI2 42
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#define SAI3 43
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#define DFSDM 44
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#define FDCAN 45
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#define LPTIM2 46
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#define LPTIM3 47
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#define LPTIM4 48
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#define LPTIM5 49
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#define SAI4 50
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#define SYSCFG 51
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#define VREF 52
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#define TMPSENS 53
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#define PMBCTRL 54
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#define HDP 55
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#define LTDC 56
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#define DSI 57
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#define IWDG2 58
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#define USBPHY 59
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#define STGENRO 60
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#define SPI6 61
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#define I2C4 62
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#define I2C6 63
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#define USART1 64
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#define RTCAPB 65
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#define TZC 66
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#define TZPC 67
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#define IWDG1 68
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#define BSEC 69
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#define STGEN 70
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#define DMA1 71
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#define DMA2 72
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#define DMAMUX 73
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#define ADC12 74
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#define USBO 75
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#define SDMMC3 76
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#define DCMI 77
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#define CRYP2 78
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#define HASH2 79
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#define RNG2 80
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#define CRC2 81
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#define HSEM 82
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#define IPCC 83
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#define GPIOA 84
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#define GPIOB 85
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#define GPIOC 86
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#define GPIOD 87
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#define GPIOE 88
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#define GPIOF 89
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#define GPIOG 90
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#define GPIOH 91
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#define GPIOI 92
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#define GPIOJ 93
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#define GPIOK 94
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#define GPIOZ 95
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#define CRYP1 96
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#define HASH1 97
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#define RNG1 98
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#define BKPSRAM 99
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#define MDMA 100
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#define DMA2D 101
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#define GPU 102
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#define ETHCK 103
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#define ETHTX 104
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#define ETHRX 105
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#define ETHMAC 106
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#define FMC 107
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#define QSPI 108
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#define SDMMC1 109
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#define SDMMC2 110
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#define CRC1 111
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#define USBH 112
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#define ETHSTP 113
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/* Kernel clocks */
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#define SDMMC1_K 114
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#define SDMMC2_K 115
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#define SDMMC3_K 116
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#define FMC_K 117
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#define QSPI_K 118
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#define ETHMAC_K 119
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#define RNG1_K 120
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#define RNG2_K 121
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#define GPU_K 122
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#define USBPHY_K 123
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#define STGEN_K 124
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#define SPDIF_K 125
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#define SPI1_K 126
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#define SPI2_K 127
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#define SPI3_K 128
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#define SPI4_K 129
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#define SPI5_K 130
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#define SPI6_K 131
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#define CEC_K 132
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#define I2C1_K 133
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#define I2C2_K 134
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#define I2C3_K 135
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#define I2C4_K 136
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#define I2C5_K 137
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#define I2C6_K 138
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#define LPTIM1_K 139
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#define LPTIM2_K 140
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#define LPTIM3_K 141
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#define LPTIM4_K 142
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#define LPTIM5_K 143
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#define USART1_K 144
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#define USART2_K 145
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#define USART3_K 146
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#define UART4_K 147
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#define UART5_K 148
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#define USART6_K 149
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#define UART7_K 150
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#define UART8_K 151
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#define DFSDM_K 152
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#define FDCAN_K 153
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#define SAI1_K 154
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#define SAI2_K 155
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#define SAI3_K 156
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#define SAI4_K 157
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#define ADC12_K 158
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#define DSI_K 159
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#define ADFSDM_K 160
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#define USBO_K 161
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#define LTDC_K 162
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/* PLL */
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#define PLL1 163
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#define PLL2 164
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#define PLL3 165
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#define PLL4 166
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/* ODF */
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#define PLL1_P 167
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#define PLL1_Q 168
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#define PLL1_R 169
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#define PLL2_P 170
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#define PLL2_Q 171
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#define PLL2_R 172
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#define PLL3_P 173
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#define PLL3_Q 174
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#define PLL3_R 175
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#define PLL4_P 176
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#define PLL4_Q 177
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#define PLL4_R 178
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/* AUX */
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#define RTC 179
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/* MCLK */
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#define CK_PER 180
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#define CK_MPU 181
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#define CK_AXI 182
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#define CK_MCU 183
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/* Time base */
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#define TIM2_K 184
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#define TIM3_K 185
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#define TIM4_K 186
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#define TIM5_K 187
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#define TIM6_K 188
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#define TIM7_K 189
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#define TIM12_K 190
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#define TIM13_K 191
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#define TIM14_K 192
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#define TIM1_K 193
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#define TIM8_K 194
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#define TIM15_K 195
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#define TIM16_K 196
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#define TIM17_K 197
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/* MCO clocks */
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#define CK_MCO1 198
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#define CK_MCO2 199
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/* TRACE & DEBUG clocks */
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#define DBG 200
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#define CK_DBG 201
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#define CK_TRACE 202
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/* DDR */
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#define DDRC1 203
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#define DDRC1LP 204
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#define DDRC2 205
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#define DDRC2LP 206
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#define DDRPHYC 207
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#define DDRPHYCLP 208
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#define DDRCAPB 209
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#define DDRCAPBLP 210
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#define AXIDCG 211
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#define DDRPHYCAPB 212
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#define DDRPHYCAPBLP 213
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#define DDRPERFM 214
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#define STM32MP1_LAST_CLK 215
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