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81f3a665ab
Convert UTF-8 chars to ASCII in cases where make sense. No Copyright or names are converted. Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Marek Behún <kabel@kernel.org>
277 lines
8.1 KiB
C
277 lines
8.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics.
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*/
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struct stm32_clock_match_data;
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/**
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* struct stm32_mux_cfg - multiplexer configuration
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*
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* @parent_names: array of string names for all possible parents
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* @num_parents: number of possible parents
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* @reg_off: register controlling multiplexer
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* @shift: shift to multiplexer bit field
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* @width: width of the multiplexer bit field
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* @mux_flags: hardware-specific flags
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* @table: array of register values corresponding to the parent
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* index
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*/
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struct stm32_mux_cfg {
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const char * const *parent_names;
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u8 num_parents;
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u32 reg_off;
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u8 shift;
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u8 width;
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u8 mux_flags;
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u32 *table;
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};
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/**
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* struct stm32_gate_cfg - gating configuration
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*
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* @reg_off: register controlling gate
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* @bit_idx: single bit controlling gate
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* @gate_flags: hardware-specific flags
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* @set_clr: 0 : normal gate, 1 : has a register to clear the gate
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*/
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struct stm32_gate_cfg {
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u32 reg_off;
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u8 bit_idx;
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u8 gate_flags;
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u8 set_clr;
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};
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/**
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* struct stm32_div_cfg - divider configuration
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*
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* @reg_off: register containing the divider
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* @shift: shift to the divider bit field
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* @width: width of the divider bit field
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* @table: array of value/divider pairs, last entry should have div = 0
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*/
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struct stm32_div_cfg {
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u32 reg_off;
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u8 shift;
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u8 width;
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u8 div_flags;
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const struct clk_div_table *table;
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};
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#define NO_STM32_MUX -1
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#define NO_STM32_DIV -1
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#define NO_STM32_GATE -1
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/**
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* struct stm32_composite_cfg - composite configuration
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*
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* @mux: index of a multiplexer
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* @gate: index of a gate
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* @div: index of a divider
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*/
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struct stm32_composite_cfg {
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int mux;
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int gate;
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int div;
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};
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/**
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* struct clock_config - clock configuration
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*
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* @id: binding id of the clock
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* @name: clock name
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* @parent_name: name of the clock parent
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* @flags: framework-specific flags
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* @sec_id: secure id (use to known if the clock is secured or not)
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* @clock_cfg: specific clock data configuration
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* @setup: specific call back to reister the clock (will use
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* clock_cfg data as input)
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*/
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struct clock_config {
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unsigned long id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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int sec_id;
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void *clock_cfg;
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struct clk *(*setup)(struct udevice *dev,
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const struct clock_config *cfg);
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};
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/**
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* struct clk_stm32_clock_data - clock data
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*
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* @num_gates: number of defined gates
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* @gates: array of gate configuration
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* @muxes: array of multiplexer configuration
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* @dividers: array of divider configuration
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*/
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struct clk_stm32_clock_data {
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unsigned int num_gates;
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const struct stm32_gate_cfg *gates;
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const struct stm32_mux_cfg *muxes;
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const struct stm32_div_cfg *dividers;
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};
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/**
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* struct stm32_clock_match_data - clock match data
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*
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* @num_gates: number of clocks
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* @tab_clocks: array of clock configuration
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* @clock_data: definition of all gates / dividers / multiplexers
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* @check_security: call back to check if clock is secured or not
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*/
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struct stm32_clock_match_data {
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unsigned int num_clocks;
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const struct clock_config *tab_clocks;
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const struct clk_stm32_clock_data *clock_data;
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int (*check_security)(void __iomem *base,
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const struct clock_config *cfg);
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};
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/**
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* struct stm32mp_rcc_priv - private struct for stm32mp clocks
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*
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* @base: base register of RCC driver
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* @gate_cpt: array of refcounting for gate with more than one
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* clocks as input. See explanation of Peripheral clock enabling
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* below.
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* @data: data for gate / divider / multiplexer configuration
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*/
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struct stm32mp_rcc_priv {
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void __iomem *base;
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u8 *gate_cpt;
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const struct clk_stm32_clock_data *data;
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};
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int stm32_rcc_init(struct udevice *dev,
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const struct stm32_clock_match_data *data);
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/**
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* STM32 Gate
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*
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* PCE (Peripheral Clock Enabling) Peripheral
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*
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* ------------------------------ ----------
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* | | | |
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* | | | PERx |
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* bus_ck | ----- | | |
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* ------------->|------------------| | | ckg_bus_perx | |
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* | | AND |-----|---------------->| |
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* | -----------| | | | |
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* | | ----- | | |
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* | | | | |
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* | ----- | | |
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* Perx_EN |-----|---| GCL | Gating | | |
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* | ----- Control | | |
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* | | Logic | | |
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* | | | | |
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* | | ----- | | |
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* | -----------| | | ckg_ker_perx | |
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* perx_ker_ck | | AND |-----|---------------->| |
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* ------------->|------------------| | | | |
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* | ----- | | |
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* | | | |
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* | | | |
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* ------------------------------ ----------
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* Each peripheral requires a bus interface clock, named ckg_bus_perx
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* (for peripheral `x').
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* Some peripherals (SAI, UART...) need also a dedicated clock for their
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* communication interface, this clock is generally asynchronous with respect to
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* the bus interface clock, and is named kernel clock (ckg_ker_perx).
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* Both clocks can be gated by one Perx_EN enable bit.
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* Then we have to manage a refcounting on gate level to avoid gate if one
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* the bus or the Kernel was enable.
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*
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* Example:
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* 1) enable the bus clock
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* --> bus_clk ref_counting = 1, gate_ref_count = 1
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* 2) enable the kernel clock
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* --> perx_ker_ck ref_counting = 1, gate_ref_count = 2
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* 3) disable kernel clock
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* ---> perx_ker_ck ref_counting = 0, gate_ref_count = 1
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* ==> then i will not gate because gate_ref_count > 0
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* 4) disable bus clock
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* --> bus_clk ref_counting = 0, gate_ref_count = 0
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* ==> then i can gate (write in the register) because
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* gate_ref_count = 0
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*/
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struct clk_stm32_gate {
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struct clk clk;
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struct stm32mp_rcc_priv *priv;
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int gate_id;
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};
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#define to_clk_stm32_gate(_clk) container_of(_clk, struct clk_stm32_gate, clk)
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struct clk *
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clk_stm32_gate_register(struct udevice *dev,
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const struct clock_config *cfg);
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struct clk *
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clk_stm32_register_composite(struct udevice *dev,
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const struct clock_config *cfg);
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struct stm32_clk_gate_cfg {
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int gate_id;
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};
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#define STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) \
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{ \
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.id = _id, \
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.sec_id = _sec_id, \
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.name = _name, \
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.parent_name = _parent, \
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.flags = _flags, \
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.clock_cfg = &(struct stm32_clk_gate_cfg) { \
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.gate_id = _gate_id, \
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}, \
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.setup = clk_stm32_gate_register, \
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}
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struct stm32_clk_composite_cfg {
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int gate_id;
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int mux_id;
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int div_id;
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};
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#define STM32_COMPOSITE(_id, _name, _flags, _sec_id, \
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_gate_id, _mux_id, _div_id) \
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{ \
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.id = _id, \
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.name = _name, \
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.sec_id = _sec_id, \
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.flags = _flags, \
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.clock_cfg = &(struct stm32_clk_composite_cfg) { \
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.gate_id = _gate_id, \
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.mux_id = _mux_id, \
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.div_id = _div_id, \
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}, \
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.setup = clk_stm32_register_composite, \
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}
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#define STM32_COMPOSITE_NOMUX(_id, _name, _parent, _flags, _sec_id, \
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_gate_id, _div_id) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.sec_id = _sec_id, \
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.flags = _flags, \
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.clock_cfg = &(struct stm32_clk_composite_cfg) { \
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.gate_id = _gate_id, \
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.mux_id = NO_STM32_MUX, \
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.div_id = _div_id, \
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}, \
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.setup = clk_stm32_register_composite, \
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}
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extern const struct clk_ops stm32_clk_ops;
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ulong clk_stm32_get_rate_by_name(const char *name);
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