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f6eb68b978
This patch adds a minimal clock driver for the Amlogic AXG SoC to handle the basic gates and PLLs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2016 - AmLogic, Inc.
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* Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
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* Copyright 2018 - BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#ifndef _ARCH_MESON_CLOCK_AXG_H_
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#define _ARCH_MESON_CLOCK_AXG_H_
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/*
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* Clock controller register offsets
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*
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* Register offsets from the data sheet are listed in comment blocks below.
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* Those offsets must be multiplied by 4 before adding them to the base address
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* to get the right value
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*/
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#define HHI_GP0_PLL_CNTL 0x40
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#define HHI_GP0_PLL_CNTL2 0x44
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#define HHI_GP0_PLL_CNTL3 0x48
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#define HHI_GP0_PLL_CNTL4 0x4c
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#define HHI_GP0_PLL_CNTL5 0x50
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#define HHI_GP0_PLL_STS 0x54
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#define HHI_GP0_PLL_CNTL1 0x58
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#define HHI_HIFI_PLL_CNTL 0x80
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#define HHI_HIFI_PLL_CNTL2 0x84
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#define HHI_HIFI_PLL_CNTL3 0x88
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#define HHI_HIFI_PLL_CNTL4 0x8C
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#define HHI_HIFI_PLL_CNTL5 0x90
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#define HHI_HIFI_PLL_STS 0x94
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#define HHI_HIFI_PLL_CNTL1 0x98
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#define HHI_XTAL_DIVN_CNTL 0xbc
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#define HHI_GCLK2_MPEG0 0xc0
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#define HHI_GCLK2_MPEG1 0xc4
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#define HHI_GCLK2_MPEG2 0xc8
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#define HHI_GCLK2_OTHER 0xd0
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#define HHI_GCLK2_AO 0xd4
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#define HHI_PCIE_PLL_CNTL 0xd8
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#define HHI_PCIE_PLL_CNTL1 0xdC
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#define HHI_PCIE_PLL_CNTL2 0xe0
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#define HHI_PCIE_PLL_CNTL3 0xe4
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#define HHI_PCIE_PLL_CNTL4 0xe8
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#define HHI_PCIE_PLL_CNTL5 0xec
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#define HHI_PCIE_PLL_CNTL6 0xf0
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#define HHI_PCIE_PLL_STS 0xf4
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#define HHI_MEM_PD_REG0 0x100
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#define HHI_VPU_MEM_PD_REG0 0x104
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#define HHI_VIID_CLK_DIV 0x128
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#define HHI_VIID_CLK_CNTL 0x12c
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#define HHI_GCLK_MPEG0 0x140
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#define HHI_GCLK_MPEG1 0x144
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#define HHI_GCLK_MPEG2 0x148
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#define HHI_GCLK_OTHER 0x150
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#define HHI_GCLK_AO 0x154
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c
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#define HHI_SYS_CPU_RESET_CNTL 0x160
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#define HHI_VID_CLK_DIV 0x164
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#define HHI_SPICC_HCLK_CNTL 0x168
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#define HHI_MPEG_CLK_CNTL 0x174
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#define HHI_VID_CLK_CNTL 0x17c
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#define HHI_TS_CLK_CNTL 0x190
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#define HHI_VID_CLK_CNTL2 0x194
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c
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#define HHI_VID_PLL_CLK_DIV 0x1a0
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#define HHI_VPU_CLK_CNTL 0x1bC
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#define HHI_VAPBCLK_CNTL 0x1F4
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#define HHI_GEN_CLK_CNTL 0x228
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#define HHI_VDIN_MEAS_CLK_CNTL 0x250
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#define HHI_NAND_CLK_CNTL 0x25C
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#define HHI_SD_EMMC_CLK_CNTL 0x264
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#define HHI_MPLL_CNTL 0x280
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#define HHI_MPLL_CNTL2 0x284
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#define HHI_MPLL_CNTL3 0x288
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#define HHI_MPLL_CNTL4 0x28C
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#define HHI_MPLL_CNTL5 0x290
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#define HHI_MPLL_CNTL6 0x294
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#define HHI_MPLL_CNTL7 0x298
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#define HHI_MPLL_CNTL8 0x29C
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#define HHI_MPLL_CNTL9 0x2A0
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#define HHI_MPLL_CNTL10 0x2A4
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#define HHI_MPLL3_CNTL0 0x2E0
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#define HHI_MPLL3_CNTL1 0x2E4
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#define HHI_PLL_TOP_MISC 0x2E8
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#define HHI_SYS_PLL_CNTL1 0x2FC
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#define HHI_SYS_PLL_CNTL 0x300
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#define HHI_SYS_PLL_CNTL2 0x304
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#define HHI_SYS_PLL_CNTL3 0x308
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#define HHI_SYS_PLL_CNTL4 0x30c
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#define HHI_SYS_PLL_CNTL5 0x310
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#define HHI_SYS_PLL_STS 0x314
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#define HHI_DPLL_TOP_I 0x318
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#define HHI_DPLL_TOP2_I 0x31C
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#endif
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