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d2166319df
Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
233 lines
8.5 KiB
C
233 lines
8.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*/
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/**
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* enum srdscr0_mask - Bit masks for SRDSCR0 (SerDes Control Register 0)
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* @SRDSCR0_DPPA: Bitmask for the DPPA (diff pk-pk swing for lane A)
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* field of the SRCSCR0
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* @SRDSCR0_DPPE: Bitmask for the DPPE (diff pk-pk swing for lane E)
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* field of the SRCSCR0
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* @SRDSCR0_DPP_1V2: Combined bitmask to set diff pk-pk swing for both lanes
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* @SRDSCR0_TXEQA_MASK: Bitmask for the TXEQA (transmit equalization for
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* lane A) field of the SRCSCR0
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* @SRDSCR0_TXEQA_SATA: Bitmask to set the TXEQA to the value used for SATA
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* @SRDSCR0_TXEQE_MASK: Bitmask for the TXEQE (transmit equalization for
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* lane E) field of the SRCSCR0
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* @SRDSCR0_TXEQE_SATA: Bitmask to set the TXEQE to the value used for SATA
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*/
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enum srdscr0_mask {
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SRDSCR0_DPPA = BIT(31 - 16),
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SRDSCR0_DPPE = BIT(31 - 20),
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SRDSCR0_DPP_1V2 = SRDSCR0_DPPE | SRDSCR0_DPPA,
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SRDSCR0_TXEQA_MASK = 0x00007000,
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SRDSCR0_TXEQA_SATA = 0x00001000,
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SRDSCR0_TXEQE_MASK = 0x00000700,
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SRDSCR0_TXEQE_SATA = 0x00000100,
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};
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/**
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* enum srdscr1_mask - Bit masks for SRDSCR1 (SerDes Control Register 1)
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* @SRDSCR1_PLLBW: Bitmask for the PLLBW (PLL bandwidth) field of SRDSCR1
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*/
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enum srdscr1_mask {
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SRDSCR1_PLLBW = BIT(31 - 25),
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};
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/**
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* enum srdscr2_mask - Bit masks for SRDSCR2 (SerDes Control Register 2)
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* @SRDSCR2_VDD_1V2: Bit mask to to set the VDD field of the SCRSCR2
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* @SRDSCR2_SEICA_MASK: Bitmask for the SEICA (Receiver electrical idle
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* detection control for lane A) field of the SRCSCR2
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* @SRDSCR2_SEICE_MASK: Bitmask for the SEICE (Receiver electrical idle
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* detection control for lane E) field of the SRCSCR2
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* @SRDSCR2_SEIC_MASK: Combined bitmask to set the receiver electrical idle
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* detection control for both lanes
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* @SRDSCR2_SEICA_SATA: Bitmask to set the SEICA field to the value used for
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* SATA
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* @SRDSCR2_SEICE_SATA: Bitmask to set the SEICE field to the value used for
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* SATA
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* @SRDSCR2_SEIC_SATA: Combined bitmask to set the value of both SEIC fields
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* to the value used for SATA
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* @SRDSCR2_SEICA_PEX: Bitmask to set the SEICA field to the value used for
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* PCI Express
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* @SRDSCR2_SEICE_PEX: Bitmask to set the SEICE field to the value used for
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* PCI Express
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* @SRDSCR2_SEIC_PEX: Combined bitmask to set the value of both SEIC fields
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* to the value used for PCI Express
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* @SRDSCR2_SEICA_SGMII: Bitmask to set the SEICA field to the value used for
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* SGMII
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* @SRDSCR2_SEICE_SGMII: Bitmask to set the SEICE field to the value used for
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* SGMII
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* @SRDSCR2_SEIC_SGMII: Combined bitmask to set the value of both SEIC fields
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* to the value used for SGMII
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*/
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enum srdscr2_mask {
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SRDSCR2_VDD_1V2 = 0x00800000,
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SRDSCR2_SEICA_MASK = 0x00001c00,
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SRDSCR2_SEICE_MASK = 0x0000001c,
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SRDSCR2_SEIC_MASK = SRDSCR2_SEICA_MASK | SRDSCR2_SEICE_MASK,
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SRDSCR2_SEICA_SATA = 0x00001400,
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SRDSCR2_SEICE_SATA = 0x00000014,
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SRDSCR2_SEIC_SATA = SRDSCR2_SEICA_SATA | SRDSCR2_SEICE_SATA,
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SRDSCR2_SEICA_PEX = 0x00001000,
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SRDSCR2_SEICE_PEX = 0x00000010,
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SRDSCR2_SEIC_PEX = SRDSCR2_SEICA_PEX | SRDSCR2_SEICE_PEX,
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SRDSCR2_SEICA_SGMII = 0x00000100,
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SRDSCR2_SEICE_SGMII = 0x00000001,
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SRDSCR2_SEIC_SGMII = SRDSCR2_SEICA_SGMII | SRDSCR2_SEICE_SGMII,
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};
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/**
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* enum srdscr3_mask - Bit masks for SRDSCR3 (SerDes Control Register 3)
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* @SRDSCR3_KFRA_SATA: Bitmask to set the KFRA field of SRDSCR3 to the
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* value used by SATA
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* @SRDSCR3_KFRE_SATA: Bitmask to set the KFRE field of SRDSCR3 to the
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* value used by SATA
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* @SRDSCR3_KFR_SATA: Combined bitmask to set both KFR fields to the
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* value used by SATA
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* @SRDSCR3_KPHA_SATA: Bitmask to set the KPHA field of SRDSCR3 to the
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* value used by SATA
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* @SRDSCR3_KPHE_SATA: Bitmask to set the KPHE field of SRDSCR3 to the
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* value used by SATA
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* @SRDSCR3_KPH_SATA: Combined bitmask to set both KPH fields to the
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* value used by SATA
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* @SRDSCR3_SDFMA_SATA_PEX: Bitmask to set the SDFMA field of SRDSCR3 to the
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* value used by SATA and PCI Express
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* @SRDSCR3_SDFME_SATA_PEX: Bitmask to set the SDFME field of SRDSCR3 to the
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* value used by SATA and PCI Express
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* @SRDSCR3_SDFM_SATA_PEX: Combined bitmask to set both SDFM fields to the
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* value used by SATA and PCI Express
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* @SRDSCR3_SDTXLA_SATA: Bitmask to set the SDTXLA field of SRDSCR3 to the
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* value used by SATA
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* @SRDSCR3_SDTXLE_SATA: Bitmask to set the SDTXLE field of SRDSCR3 to the
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* value used by SATA
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* @SRDSCR3_SDTXL_SATA: Combined bitmask to set both SDTXL fields to the
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* value used by SATA
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*
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* KFRA = 'Kfr' gain selection in the CDR for lane A
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* KFRE = 'Kfr' gain selection in the CDR for lane E
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* SDFMA = Bandwidth of digital filter for lane A
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* SDFME = Bandwidth of digital filter for lane E
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* SDTXLA = Lane A transmitter amplitude levels
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* SDTXLE = Lane E transmitter amplitude levels
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*/
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enum srdscr3_mask {
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SRDSCR3_KFRA_SATA = 0x10000000,
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SRDSCR3_KFRE_SATA = 0x00100000,
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SRDSCR3_KFR_SATA = SRDSCR3_KFRA_SATA | SRDSCR3_KFRE_SATA,
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SRDSCR3_KPHA_SATA = 0x04000000,
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SRDSCR3_KPHE_SATA = 0x00040000,
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SRDSCR3_KPH_SATA = SRDSCR3_KPHA_SATA | SRDSCR3_KPHE_SATA,
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SRDSCR3_SDFMA_SATA_PEX = 0x01000000,
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SRDSCR3_SDFME_SATA_PEX = 0x00010000,
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SRDSCR3_SDFM_SATA_PEX = SRDSCR3_SDFMA_SATA_PEX | SRDSCR3_SDFME_SATA_PEX,
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SRDSCR3_SDTXLA_SATA = 0x00000500,
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SRDSCR3_SDTXLE_SATA = 0x00000005,
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SRDSCR3_SDTXL_SATA = SRDSCR3_SDTXLA_SATA | SRDSCR3_SDTXLE_SATA,
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};
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/**
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* enum srdscr4_mask - Bit masks for SRDSCR4 (SerDes Control Register 4)
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* @SRDSCR4_PROTA_SATA: Bitmask to set the PROTA field of SRDSCR4 to the
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* value used by SATA
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* @SRDSCR4_PROTE_SATA: Bitmask to set the PROTE field of SRDSCR4 to the
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* value used by SATA
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* @SRDSCR4_PROT_SATA: Combined bitmask to set both PROT fields to the
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* value used by SATA
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* @SRDSCR4_PROTA_PEX: Bitmask to set the PROTA field of SRDSCR4 to the
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* value used by PCI Express
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* @SRDSCR4_PROTE_PEX: Bitmask to set the PROTE field of SRDSCR4 to the
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* value used by PCI Express
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* @SRDSCR4_PROT_PEX: Combined bitmask to set both PROT fields to the
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* value used by PCI Express
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* @SRDSCR4_PROTA_SGMII: Bitmask to set the PROTA field of SRDSCR4 to the
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* value used by SGMII
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* @SRDSCR4_PROTE_SGMII: Bitmask to set the PROTE field of SRDSCR4 to the
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* value used by SGMII
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* @SRDSCR4_PROT_SGMII: Combined bitmask to set both PROT fields to the
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* value used by SGMII
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* @SRDSCR4_PLANE_X2: Bitmask to set the PLANE field of SRDSCR4
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* @SRDSCR4_RFCKS_100: Bitmask to set the RFCKS field of SRDSCR4 to the
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* value 100Mhz
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* @SRDSCR4_RFCKS_125: Bitmask to set the RFCKS field of SRDSCR4 to the
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* value 125Mhz
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* @SRDSCR4_RFCKS_150: Bitmask to set the RFCKS field of SRDSCR4 to the
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* value 150Mhz
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*
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* PROTA = Lane A protocol select
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* PROTE = Lane E protocol select
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* PLAME = Number of PCI Express lanes
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*/
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enum srdscr4_mask {
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SRDSCR4_PROTA_SATA = 0x00000800,
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SRDSCR4_PROTE_SATA = 0x00000008,
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SRDSCR4_PROT_SATA = SRDSCR4_PROTA_SATA | SRDSCR4_PROTE_SATA,
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SRDSCR4_PROTA_PEX = 0x00000100,
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SRDSCR4_PROTE_PEX = 0x00000001,
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SRDSCR4_PROT_PEX = SRDSCR4_PROTA_PEX | SRDSCR4_PROTE_PEX,
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SRDSCR4_PROTA_SGMII = 0x00000500,
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SRDSCR4_PROTE_SGMII = 0x00000005,
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SRDSCR4_PROT_SGMII = SRDSCR4_PROTA_SGMII | SRDSCR4_PROTE_SGMII,
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SRDSCR4_PLANE_X2 = 0x01000000,
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SRDSCR4_RFCKS_100 = (0 << 28),
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SRDSCR4_RFCKS_125 = (1 << 28),
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SRDSCR4_RFCKS_150 = (3 << 28),
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};
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/**
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* enum srdsrstctl_mask - Bit masks for SRDSRSTCTL (SerDes Reset Control Register)
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* @SRDSRSTCTL_RST: Bitmask for the RST (Software reset) field of the
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* SRDSRSTCTL
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* @SRDSRSTCTL_SATA_RESET: Bitmask for the SATA_RESET (SATA reset) field of the
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* SRDSRSTCTL
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*/
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enum srdsrstctl_mask {
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SRDSRSTCTL_RST = 0x80000000,
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SRDSRSTCTL_SATA_RESET = 0xf,
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};
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/**
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* struct mpc83xx_serdes_regs - Register map of the SerDes controller
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* @srdscr0: SerDes Control Register 0
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* @srdscr1: SerDes Control Register 1
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* @srdscr2: SerDes Control Register 2
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* @srdscr3: SerDes Control Register 3
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* @srdscr4: SerDes Control Register 4
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* @fill0: Reserved space in the register map
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* @srdsrstctl: SerDes Reset Control Register
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*/
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struct mpc83xx_serdes_regs {
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u32 srdscr0;
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u32 srdscr1;
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u32 srdscr2;
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u32 srdscr3;
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u32 srdscr4;
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u8 fill0[12];
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u32 srdsrstctl;
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};
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/**
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* enum pex_type - Types of PCI Express
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* @PEX_X1: PCI Express in x1 mode
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* @PEX_X2: PCI Express in x2 mode
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*/
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enum pex_type {
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PEX_X1,
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PEX_X2,
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};
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