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404 lines
10 KiB
ArmAsm
404 lines
10 KiB
ArmAsm
/* Copyright (C) 2003-2007 Analog Devices Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License.
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*/
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#define ASSEMBLY
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#include <asm/linkage.h>
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#include <asm/cplb.h>
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#include <config.h>
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#include <asm/blackfin.h>
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.text
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/* This is an external function being called by the user
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* application through __flush_cache_all. Currently this function
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* serves the purpose of flushing all the pending writes in
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* in the instruction cache.
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*/
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ENTRY(_flush_instruction_cache)
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[--SP] = ( R7:6, P5:4 );
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LINK 12;
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SP += -12;
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P5.H = (ICPLB_ADDR0 >> 16);
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P5.L = (ICPLB_ADDR0 & 0xFFFF);
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P4.H = (ICPLB_DATA0 >> 16);
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P4.L = (ICPLB_DATA0 & 0xFFFF);
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R7 = CPLB_VALID | CPLB_L1_CHBL;
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R6 = 16;
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inext: R0 = [P5++];
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R1 = [P4++];
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[--SP] = RETS;
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CALL _icplb_flush; /* R0 = page, R1 = data*/
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RETS = [SP++];
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iskip: R6 += -1;
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CC = R6;
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IF CC JUMP inext;
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SSYNC;
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SP += 12;
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UNLINK;
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( R7:6, P5:4 ) = [SP++];
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RTS;
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/* This is an internal function to flush all pending
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* writes in the cache associated with a particular ICPLB.
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*
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* R0 - page's start address
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* R1 - CPLB's data field.
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*/
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.align 2
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ENTRY(_icplb_flush)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = LC0;
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[--SP] = LT0;
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[--SP] = LB0;
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[--SP] = LC1;
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[--SP] = LT1;
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[--SP] = LB1;
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/* If it's a 1K or 4K page, then it's quickest to
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* just systematically flush all the addresses in
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* the page, regardless of whether they're in the
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* cache, or dirty. If it's a 1M or 4M page, there
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* are too many addresses, and we have to search the
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* cache for lines corresponding to the page.
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*/
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CC = BITTST(R1, 17); /* 1MB or 4MB */
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IF !CC JUMP iflush_whole_page;
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/* We're only interested in the page's size, so extract
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* this from the CPLB (bits 17:16), and scale to give an
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* offset into the page_size and page_prefix tables.
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*/
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R1 <<= 14;
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R1 >>= 30;
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R1 <<= 2;
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/* We can also determine the sub-bank used, because this is
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* taken from bits 13:12 of the address.
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*/
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R3 = ((12<<8)|2); /* Extraction pattern */
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nop; /* Anamoly 05000209 */
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R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits */
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/* Save in extraction pattern for later deposit. */
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R3.H = R4.L << 0;
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/* So:
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* R0 = Page start
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* R1 = Page length (actually, offset into size/prefix tables)
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* R3 = sub-bank deposit values
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*
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* The cache has 2 Ways, and 64 sets, so we iterate through
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* the sets, accessing the tag for each Way, for our Bank and
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* sub-bank, looking for dirty, valid tags that match our
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* address prefix.
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*/
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P5.L = (ITEST_COMMAND & 0xFFFF);
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P5.H = (ITEST_COMMAND >> 16);
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P4.L = (ITEST_DATA0 & 0xFFFF);
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P4.H = (ITEST_DATA0 >> 16);
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P0.L = page_prefix_table;
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P0.H = page_prefix_table;
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P1 = R1;
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R5 = 0; /* Set counter*/
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P0 = P1 + P0;
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R4 = [P0]; /* This is the address prefix*/
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/* We're reading (bit 1==0) the tag (bit 2==0), and we
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* don't care about which double-word, since we're only
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* fetching tags, so we only have to set Set, Bank,
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* Sub-bank and Way.
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*/
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P2 = 4;
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LSETUP (ifs1, ife1) LC1 = P2;
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ifs1: P0 = 32; /* iterate over all sets*/
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LSETUP (ifs0, ife0) LC0 = P0;
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ifs0: R6 = R5 << 5; /* Combine set*/
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R6.H = R3.H << 0 ; /* and sub-bank*/
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[P5] = R6; /* Issue Command*/
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SSYNC; /* CSYNC will not work here :(*/
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R7 = [P4]; /* and read Tag.*/
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CC = BITTST(R7, 0); /* Check if valid*/
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IF !CC JUMP ifskip; /* and skip if not.*/
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/* Compare against the page address. First, plant bits 13:12
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* into the tag, since those aren't part of the returned data.
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*/
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R7 = DEPOSIT(R7, R3); /* set 13:12*/
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R1 = R7 & R4; /* Mask off lower bits*/
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CC = R1 == R0; /* Compare against page start.*/
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IF !CC JUMP ifskip; /* Skip it if it doesn't match.*/
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/* Tag address matches against page, so this is an entry
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* we must flush.
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*/
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R7 >>= 10; /* Mask off the non-address bits*/
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R7 <<= 10;
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P3 = R7;
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IFLUSH [P3]; /* And flush the entry*/
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ifskip:
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ife0: R5 += 1; /* Advance to next Set*/
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ife1: NOP;
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ifinished:
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SSYNC; /* Ensure the data gets out to mem.*/
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/*Finished. Restore context.*/
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LB1 = [SP++];
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LT1 = [SP++];
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LC1 = [SP++];
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LB0 = [SP++];
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LT0 = [SP++];
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LC0 = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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iflush_whole_page:
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/* It's a 1K or 4K page, so quicker to just flush the
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* entire page.
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*/
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P1 = 32; /* For 1K pages*/
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P2 = P1 << 2; /* For 4K pages*/
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P0 = R0; /* Start of page*/
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CC = BITTST(R1, 16); /* Whether 1K or 4K*/
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IF CC P1 = P2;
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P1 += -1; /* Unroll one iteration*/
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SSYNC;
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IFLUSH [P0++]; /* because CSYNC can't end loops.*/
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LSETUP (isall, ieall) LC0 = P1;
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isall:IFLUSH [P0++];
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ieall: NOP;
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SSYNC;
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JUMP ifinished;
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/* This is an external function being called by the user
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* application through __flush_cache_all. Currently this function
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* serves the purpose of flushing all the pending writes in
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* in the data cache.
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*/
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ENTRY(_flush_data_cache)
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[--SP] = ( R7:6, P5:4 );
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LINK 12;
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SP += -12;
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P5.H = (DCPLB_ADDR0 >> 16);
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P5.L = (DCPLB_ADDR0 & 0xFFFF);
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P4.H = (DCPLB_DATA0 >> 16);
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P4.L = (DCPLB_DATA0 & 0xFFFF);
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R7 = CPLB_VALID | CPLB_L1_CHBL | CPLB_DIRTY (Z);
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R6 = 16;
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next: R0 = [P5++];
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R1 = [P4++];
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CC = BITTST(R1, 14); /* Is it write-through?*/
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IF CC JUMP skip; /* If so, ignore it.*/
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R2 = R1 & R7; /* Is it a dirty, cached page?*/
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CC = R2;
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IF !CC JUMP skip; /* If not, ignore it.*/
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[--SP] = RETS;
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CALL _dcplb_flush; /* R0 = page, R1 = data*/
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RETS = [SP++];
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skip: R6 += -1;
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CC = R6;
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IF CC JUMP next;
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SSYNC;
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SP += 12;
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UNLINK;
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( R7:6, P5:4 ) = [SP++];
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RTS;
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/* This is an internal function to flush all pending
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* writes in the cache associated with a particular DCPLB.
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*
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* R0 - page's start address
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* R1 - CPLB's data field.
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*/
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.align 2
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ENTRY(_dcplb_flush)
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[--SP] = ( R7:0, P5:0 );
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[--SP] = LC0;
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[--SP] = LT0;
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[--SP] = LB0;
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[--SP] = LC1;
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[--SP] = LT1;
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[--SP] = LB1;
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/* If it's a 1K or 4K page, then it's quickest to
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* just systematically flush all the addresses in
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* the page, regardless of whether they're in the
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* cache, or dirty. If it's a 1M or 4M page, there
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* are too many addresses, and we have to search the
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* cache for lines corresponding to the page.
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*/
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CC = BITTST(R1, 17); /* 1MB or 4MB */
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IF !CC JUMP dflush_whole_page;
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/* We're only interested in the page's size, so extract
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* this from the CPLB (bits 17:16), and scale to give an
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* offset into the page_size and page_prefix tables.
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*/
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R1 <<= 14;
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R1 >>= 30;
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R1 <<= 2;
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/* The page could be mapped into Bank A or Bank B, depending
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* on (a) whether both banks are configured as cache, and
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* (b) on whether address bit A[x] is set. x is determined
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* by DCBS in DMEM_CONTROL
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*/
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R2 = 0; /* Default to Bank A (Bank B would be 1)*/
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P0.L = (DMEM_CONTROL & 0xFFFF);
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P0.H = (DMEM_CONTROL >> 16);
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R3 = [P0]; /* If Bank B is not enabled as cache*/
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CC = BITTST(R3, 2); /* then Bank A is our only option.*/
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IF CC JUMP bank_chosen;
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R4 = 1<<14; /* If DCBS==0, use A[14].*/
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R5 = R4 << 7; /* If DCBS==1, use A[23];*/
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CC = BITTST(R3, 4);
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IF CC R4 = R5; /* R4 now has either bit 14 or bit 23 set.*/
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R5 = R0 & R4; /* Use it to test the Page address*/
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CC = R5; /* and if that bit is set, we use Bank B,*/
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R2 = CC; /* else we use Bank A.*/
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R2 <<= 23; /* The Bank selection's at posn 23.*/
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bank_chosen:
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/* We can also determine the sub-bank used, because this is
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* taken from bits 13:12 of the address.
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*/
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R3 = ((12<<8)|2); /* Extraction pattern */
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nop; /*Anamoly 05000209*/
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R4 = EXTRACT(R0, R3.L) (Z); /* Extract bits*/
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/* Save in extraction pattern for later deposit.*/
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R3.H = R4.L << 0;
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/* So:
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* R0 = Page start
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* R1 = Page length (actually, offset into size/prefix tables)
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* R2 = Bank select mask
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* R3 = sub-bank deposit values
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*
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* The cache has 2 Ways, and 64 sets, so we iterate through
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* the sets, accessing the tag for each Way, for our Bank and
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* sub-bank, looking for dirty, valid tags that match our
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* address prefix.
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*/
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P5.L = (DTEST_COMMAND & 0xFFFF);
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P5.H = (DTEST_COMMAND >> 16);
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P4.L = (DTEST_DATA0 & 0xFFFF);
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P4.H = (DTEST_DATA0 >> 16);
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P0.L = page_prefix_table;
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P0.H = page_prefix_table;
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P1 = R1;
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R5 = 0; /* Set counter*/
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P0 = P1 + P0;
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R4 = [P0]; /* This is the address prefix*/
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/* We're reading (bit 1==0) the tag (bit 2==0), and we
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* don't care about which double-word, since we're only
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* fetching tags, so we only have to set Set, Bank,
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* Sub-bank and Way.
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*/
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P2 = 2;
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LSETUP (fs1, fe1) LC1 = P2;
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fs1: P0 = 64; /* iterate over all sets*/
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LSETUP (fs0, fe0) LC0 = P0;
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fs0: R6 = R5 << 5; /* Combine set*/
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R6.H = R3.H << 0 ; /* and sub-bank*/
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R6 = R6 | R2; /* and Bank. Leave Way==0 at first.*/
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BITSET(R6,14);
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[P5] = R6; /* Issue Command*/
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SSYNC;
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R7 = [P4]; /* and read Tag.*/
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CC = BITTST(R7, 0); /* Check if valid*/
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IF !CC JUMP fskip; /* and skip if not.*/
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CC = BITTST(R7, 1); /* Check if dirty*/
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IF !CC JUMP fskip; /* and skip if not.*/
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/* Compare against the page address. First, plant bits 13:12
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* into the tag, since those aren't part of the returned data.
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*/
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R7 = DEPOSIT(R7, R3); /* set 13:12*/
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R1 = R7 & R4; /* Mask off lower bits*/
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CC = R1 == R0; /* Compare against page start.*/
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IF !CC JUMP fskip; /* Skip it if it doesn't match.*/
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/* Tag address matches against page, so this is an entry
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* we must flush.
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*/
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R7 >>= 10; /* Mask off the non-address bits*/
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R7 <<= 10;
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P3 = R7;
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SSYNC;
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FLUSHINV [P3]; /* And flush the entry*/
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fskip:
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fe0: R5 += 1; /* Advance to next Set*/
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fe1: BITSET(R2, 26); /* Go to next Way.*/
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dfinished:
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SSYNC; /* Ensure the data gets out to mem.*/
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/*Finished. Restore context.*/
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LB1 = [SP++];
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LT1 = [SP++];
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LC1 = [SP++];
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LB0 = [SP++];
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LT0 = [SP++];
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LC0 = [SP++];
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( R7:0, P5:0 ) = [SP++];
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RTS;
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dflush_whole_page:
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/* It's a 1K or 4K page, so quicker to just flush the
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* entire page.
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*/
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P1 = 32; /* For 1K pages*/
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P2 = P1 << 2; /* For 4K pages*/
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P0 = R0; /* Start of page*/
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CC = BITTST(R1, 16); /* Whether 1K or 4K*/
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IF CC P1 = P2;
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P1 += -1; /* Unroll one iteration*/
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SSYNC;
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FLUSHINV [P0++]; /* because CSYNC can't end loops.*/
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LSETUP (eall, eall) LC0 = P1;
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eall: FLUSHINV [P0++];
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SSYNC;
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JUMP dfinished;
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.align 4;
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page_prefix_table:
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.byte4 0xFFFFFC00; /* 1K */
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.byte4 0xFFFFF000; /* 4K */
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.byte4 0xFFF00000; /* 1M */
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.byte4 0xFFC00000; /* 4M */
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.page_prefix_table.end:
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