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7c966a8bdf
Configuration defines should be preceeded with CONFIG_SYS_. Renamed some at91 specific defines to conform to this naming convention: AT91_CPU_NAME to CONFIG_SYS_AT91_CPU_NAME AT91_MAIN_CLOCK to CONFIG_SYS_AT91_MAIN_CLOCK Signed-off-by: Achim Ehrlich <aehrlich@taskit.de>
335 lines
8.4 KiB
C
335 lines
8.4 KiB
C
/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian.pop@leadtechdesign.com>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/sizes.h>
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#include <asm/arch/at91sam9g45.h>
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#include <asm/arch/at91sam9_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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#include <lcd.h>
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#include <atmel_lcdc.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#ifdef CONFIG_CMD_NAND
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static void at91sam9m10g45ek_nand_hw_init(void)
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{
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unsigned long csa;
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/* Enable CS3 */
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csa = at91_sys_read(AT91_MATRIX_EBICSA);
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at91_sys_write(AT91_MATRIX_EBICSA,
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csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
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/* Configure SMC CS3 for NAND/SmartMedia */
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at91_sys_write(AT91_SMC_SETUP(3),
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AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
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AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
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at91_sys_write(AT91_SMC_PULSE(3),
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AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
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AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
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at91_sys_write(AT91_SMC_CYCLE(3),
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AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
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at91_sys_write(AT91_SMC_MODE(3),
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AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
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AT91_SMC_EXNWMODE_DISABLE |
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#ifdef CONFIG_SYS_NAND_DBW_16
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AT91_SMC_DBW_16 |
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#else /* CONFIG_SYS_NAND_DBW_8 */
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AT91_SMC_DBW_8 |
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#endif
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AT91_SMC_TDF_(3));
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
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/* Configure RDY/BSY */
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at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
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/* Enable NandFlash */
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at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
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}
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#endif
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#ifdef CONFIG_MACB
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static void at91sam9m10g45ek_macb_hw_init(void)
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{
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unsigned long rstc;
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/* Enable clock */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
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/*
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* Disable pull-up on:
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* RXDV (PA15) => PHY normal mode (not Test mode)
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* ERX0 (PA12) => PHY ADDR0
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* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA12) |
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pin_to_mask(AT91_PIN_PA13),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
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rstc = at91_sys_read(AT91_RSTC_MR);
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/* Need to reset PHY -> 500ms reset */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(AT91_RSTC_ERSTL & (0x0D << 8)) |
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AT91_RSTC_URSTEN);
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at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
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/* Wait for end hardware reset */
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while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
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/* Restore NRST value */
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at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
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(rstc) |
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AT91_RSTC_URSTEN);
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA12) |
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pin_to_mask(AT91_PIN_PA13),
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pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
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at91_macb_hw_init();
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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vl_col: 480,
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vl_row: 272,
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vl_clk: 9000000,
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vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
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ATMEL_LCDC_INVFRAME_NORMAL,
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vl_bpix: 3,
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vl_tft: 1,
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vl_hsync_len: 45,
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vl_left_margin: 1,
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vl_right_margin:1,
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vl_vsync_len: 1,
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vl_upper_margin:40,
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vl_lower_margin:1,
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mmio: AT91SAM9G45_LCDC_BASE,
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};
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void lcd_enable(void)
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{
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at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
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}
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static void at91sam9m10g45ek_lcd_hw_init(void)
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{
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at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
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at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
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at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
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at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
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at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
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at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
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at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
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at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
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at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
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at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
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at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
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at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
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at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
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at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
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at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
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at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
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at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
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at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
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at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
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at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
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at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
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at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
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at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
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at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
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at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
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at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
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at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
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at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
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gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
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}
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#ifdef CONFIG_LCD_INFO
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#include <nand.h>
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#include <version.h>
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void lcd_show_board_info(void)
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{
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ulong dram_size, nand_size;
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int i;
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char temp[32];
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lcd_printf ("%s\n", U_BOOT_VERSION);
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lcd_printf ("(C) 2008 ATMEL Corp\n");
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lcd_printf ("at91support@atmel.com\n");
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lcd_printf ("%s CPU at %s MHz\n",
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CONFIG_SYS_AT91_CPU_NAME,
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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dram_size += gd->bd->bi_dram[i].size;
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nand_size = 0;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_size += nand_info[i].size;
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lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
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dram_size >> 20,
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nand_size >> 20 );
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}
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#endif /* CONFIG_LCD_INFO */
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#endif
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int board_init(void)
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{
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/* Enable Ctrlc */
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console_init_f();
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/* arch number of AT91SAM9M10G45EK-Board */
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#ifdef CONFIG_AT91SAM9M10G45EK
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
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#elif defined CONFIG_AT91SAM9G45EKES
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gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
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#endif
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/* adress of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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at91_serial_hw_init();
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#ifdef CONFIG_CMD_NAND
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at91sam9m10g45ek_nand_hw_init();
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#endif
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#ifdef CONFIG_HAS_DATAFLASH
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at91_spi0_hw_init(1 << 0);
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#endif
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#ifdef CONFIG_ATMEL_SPI
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at91_spi0_hw_init(1 << 4);
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#endif
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#ifdef CONFIG_MACB
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at91sam9m10g45ek_macb_hw_init();
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#endif
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#ifdef CONFIG_LCD
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at91sam9m10g45ek_lcd_hw_init();
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_RESET_PHY_R
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void reset_phy(void)
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{
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#ifdef CONFIG_MACB
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/*
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* Initialize ethernet HW addr prior to starting Linux,
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* needed for nfsroot
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*/
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eth_init(gd->bd);
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#endif
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_MACB
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rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
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#endif
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return rc;
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}
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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#include <spi.h>
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs < 2;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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switch(slave->cs) {
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case 1:
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at91_set_gpio_output(AT91_PIN_PB18, 0);
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break;
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case 0:
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default:
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at91_set_gpio_output(AT91_PIN_PB3, 0);
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break;
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}
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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switch(slave->cs) {
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case 1:
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at91_set_gpio_output(AT91_PIN_PB18, 1);
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break;
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case 0:
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default:
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at91_set_gpio_output(AT91_PIN_PB3, 1);
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break;
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}
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}
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#endif /* CONFIG_ATMEL_SPI */
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