Marek Vasut 70ed80af46 ddr: altera: Zero DM IN delay in scc_mgr_zero_group() ...

This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

2016-04-20 11:28:45 +02:00

..

altera

ddr: altera: Zero DM IN delay in scc_mgr_zero_group()

2016-04-20 11:28:45 +02:00

fsl

Fix typo choosen in comments and printf logs

2016-03-27 09:12:23 -04:00

marvell

arm: mvebu: Fix ddr3_init() cpu config

2016-03-24 09:36:40 +01:00

microchip

drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.

2016-02-01 22:14:01 +01:00