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d3ee9dbd59
Per NXP requirement, we rename all the NXP EdgeLock Secure Enclave code including comment, folder and API name to ELE to align. Signed-off-by: Peng Fan <peng.fan@nxp.com>
267 lines
6.0 KiB
C
267 lines
6.0 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Copyright 2021 NXP
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*/
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#include <log.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <linux/delay.h>
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#include "upower_api.h"
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#define UPOWER_AP_MU1_ADDR 0x29280000
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#define PS_RTD BIT(0)
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#define PS_DSP BIT(1)
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#define PS_A35_0 BIT(2)
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#define PS_A35_1 BIT(3)
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#define PS_L2 BIT(4)
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#define PS_FAST_NIC BIT(5)
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#define PS_APD_PERIPH BIT(6)
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#define PS_GPU3D BIT(7)
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#define PS_HIFI4 BIT(8)
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#define PS_DDR GENMASK(12, 9)
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#define PS_PXP_EPDC BIT(13)
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#define PS_MIPI_DSI BIT(14)
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#define PS_MIPI_CSI BIT(15)
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#define PS_NIC_LPAV BIT(16)
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#define PS_FUSION_AO BIT(17)
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#define PS_FUSE BIT(18)
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#define PS_UPOWER BIT(19)
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static struct mu_type *muptr = (struct mu_type *)UPOWER_AP_MU1_ADDR;
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void upower_wait_resp(void)
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{
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while (!(readl(&muptr->rsr) & BIT(0))) {
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debug("%s: poll the mu:%x\n", __func__, readl(&muptr->rsr));
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udelay(100);
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}
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upwr_txrx_isr();
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}
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u32 upower_status(int status)
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{
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u32 ret = -1;
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switch (status) {
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case 0:
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debug("%s: finished successfully!\n", __func__);
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ret = 0;
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break;
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case -1:
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printf("%s: memory allocation or resource failed!\n", __func__);
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break;
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case -2:
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printf("%s: invalid argument!\n", __func__);
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break;
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case -3:
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printf("%s: called in an invalid API state!\n", __func__);
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break;
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default:
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printf("%s: invalid return status\n", __func__);
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break;
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}
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return ret;
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}
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void user_upwr_rdy_callb(u32 soc, u32 vmajor, u32 vminor)
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{
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printf("%s: soc=%x\n", __func__, soc);
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printf("%s: RAM version:%d.%d\n", __func__, vmajor, vminor);
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}
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int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val)
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{
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int ret, ret_val;
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enum upwr_resp err_code;
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ret = upwr_xcp_i2c_access(0x32, 1, 1, reg_addr, reg_val, NULL);
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if (ret) {
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printf("pmic i2c write failed ret %d\n", ret);
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return ret;
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}
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upower_wait_resp();
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ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
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if (ret != UPWR_REQ_OK) {
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printf("i2c poll Failure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
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return ret;
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}
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debug("PMIC write reg[0x%x], val[0x%x]\n", reg_addr, reg_val);
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return 0;
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}
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int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val)
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{
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int ret, ret_val;
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enum upwr_resp err_code;
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if (!reg_val)
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return -1;
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ret = upwr_xcp_i2c_access(0x32, -1, 1, reg_addr, 0, NULL);
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if (ret) {
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printf("pmic i2c read failed ret %d\n", ret);
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return ret;
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}
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upower_wait_resp();
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ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
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if (ret != UPWR_REQ_OK) {
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printf("i2c poll Failure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
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return ret;
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}
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*reg_val = ret_val;
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debug("PMIC read reg[0x%x], val[0x%x]\n", reg_addr, *reg_val);
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return 0;
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}
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int upower_init(void)
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{
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u32 fw_major, fw_minor, fw_vfixes;
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u32 soc_id;
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int status;
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enum upwr_resp err_code;
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u32 swton;
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u64 memon;
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int ret, ret_val;
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do {
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status = upwr_init(1, muptr);
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if (upower_status(status)) {
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printf("%s: upower init failure\n", __func__);
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break;
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}
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soc_id = upwr_rom_version(&fw_major, &fw_minor, &fw_vfixes);
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if (!soc_id) {
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printf("%s:, soc_id not initialized\n", __func__);
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break;
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}
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printf("%s: soc_id=%d\n", __func__, soc_id);
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printf("%s: version:%d.%d.%d\n", __func__, fw_major, fw_minor, fw_vfixes);
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printf("%s: start uPower RAM service\n", __func__);
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status = upwr_start(1, user_upwr_rdy_callb);
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upower_wait_resp();
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if (upower_status(status)) {
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printf("%s: upower init failure\n", __func__);
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break;
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}
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} while (0);
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swton = PS_UPOWER | PS_FUSE | PS_FUSION_AO | PS_NIC_LPAV | PS_PXP_EPDC | PS_DDR |
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PS_HIFI4 | PS_GPU3D | PS_MIPI_DSI;
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ret = upwr_pwm_power_on(&swton, NULL, NULL);
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if (ret)
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printf("Turn on switches fail %d\n", ret);
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else
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printf("Turning on switches...\n");
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upower_wait_resp();
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ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000);
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if (ret != UPWR_REQ_OK)
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printf("Turn on switches faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
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else
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printf("Turn on switches ok\n");
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/*
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* Ascending Order -> bit [0:54)
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* CA35 Core 0 L1 cache
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* CA35 Core 1 L1 cache
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* L2 Cache 0
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* L2 Cache 1
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* L2 Cache victim/tag
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* CAAM Secure RAM
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* DMA1 RAM
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* FlexSPI2 FIFO, Buffer
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* SRAM0
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* AD ROM
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* USB0 TX/RX RAM
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* uSDHC0 FIFO RAM
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* uSDHC1 FIFO RAM
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* uSDHC2 FIFO and USB1 TX/RX RAM
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* GIC RAM
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* ENET TX FIXO
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* Reserved(Brainshift)
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* DCNano Tile2Linear and RGB Correction
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* DCNano Cursor and FIFO
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* EPDC LUT
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* EPDC FIFO
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* DMA2 RAM
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* GPU2D RAM Group 1
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* GPU2D RAM Group 2
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* GPU3D RAM Group 1
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* GPU3D RAM Group 2
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* HIFI4 Caches, IRAM, DRAM
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* ISI Buffers
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* MIPI-CSI FIFO
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* MIPI-DSI FIFO
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* PXP Caches, Buffers
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* SRAM1
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* Casper RAM
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* DMA0 RAM
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* FlexCAN RAM
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* FlexSPI0 FIFO, Buffer
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* FlexSPI1 FIFO, Buffer
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* CM33 Cache
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* PowerQuad RAM
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* ETF RAM
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* ELE PKC, Data RAM1, Inst RAM0/1
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* ELE ROM
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* uPower IRAM/DRAM
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* uPower ROM
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* CM33 ROM
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* SSRAM Partition 0
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* SSRAM Partition 1
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* SSRAM Partition 2,3,4
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* SSRAM Partition 5
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* SSRAM Partition 6
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* SSRAM Partition 7_a(128KB)
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* SSRAM Partition 7_b(64KB)
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* SSRAM Partition 7_c(64KB)
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* ELE Data RAM0, Inst RAM2
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*/
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/* MIPI-CSI FIFO BIT28 not set */
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memon = 0x3FFFFFEFFFFFFCUL;
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ret = upwr_pwm_power_on(NULL, (const uint32_t *)&memon, NULL);
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if (ret)
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printf("Turn on memories fail %d\n", ret);
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else
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printf("Turning on memories...\n");
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upower_wait_resp();
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ret = upwr_poll_req_status(UPWR_SG_PWRMGMT, NULL, &err_code, &ret_val, 1000);
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if (ret != UPWR_REQ_OK)
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printf("Turn on memories faliure %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
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else
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printf("Turn on memories ok\n");
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mdelay(1);
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ret = upwr_xcp_set_ddr_retention(APD_DOMAIN, 0, NULL);
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if (ret)
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printf("Clear DDR retention fail %d\n", ret);
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else
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printf("Clearing DDR retention...\n");
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upower_wait_resp();
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ret = upwr_poll_req_status(UPWR_SG_EXCEPT, NULL, &err_code, &ret_val, 1000);
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if (ret != UPWR_REQ_OK)
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printf("Clear DDR retention fail %d, err_code %d, ret_val 0x%x\n", ret, err_code, ret_val);
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else
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printf("Clear DDR retention ok\n");
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return 0;
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}
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