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			163 lines
		
	
	
		
			4.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			163 lines
		
	
	
		
			4.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * (C) Copyright 2000
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|  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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|  *
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|  * See file CREDITS for list of people who contributed to this
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|  * project.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 of
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|  * the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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|  * MA 02111-1307 USA
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|  */
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| 
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| 
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| #include <common.h>
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| #include <mpc8xx.h>
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| static long int dram_size (long int, long int *, long int);
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| #define	_NOT_USED_	0xFFFFCC25
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| 
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| const uint sdram_table[] =
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| {
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| 	/*
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| 	 * Single Read. (Offset 00h in UPMA RAM)
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| 	 */
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| 	0x0F03CC04, 0x00ACCC24, 0x1FF74C20, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 
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| 	/*
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| 	 * Burst Read. (Offset 08h in UPMA RAM)
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| 	 */
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| 	0x0F03CC04, 0x00ACCC24, 0x00FFCC20, 0x00FFCC20,
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| 	0x01FFCC20, 0x1FF74C20, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 
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| 	/*
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| 	 * Single Write. (Offset 18h in UPMA RAM)
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| 	 */
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| 	0x0F03CC02, 0x00AC0C24, 0x1FF74C25, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 
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| 	/*
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| 	 * Burst Write. (Offset 20h in UPMA RAM)
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| 	 */
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| 	0x0F03CC00, 0x00AC0C20, 0x00FFFC20, 0x00FFFC22,
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| 	0x01FFFC24, 0x1FF74C25, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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| 
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| 	/*
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| 	 * Refresh. (Offset 30h in UPMA RAM)
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| 	 * (Initialization code at 0x36)
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| 	 */
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| 	0x0FF0CC24, 0xFFFFCC24, _NOT_USED_, _NOT_USED_,
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| 	_NOT_USED_, _NOT_USED_, 0xEFFB8C34, 0x0FF74C34,
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| 	0x0FFACCB4, 0x0FF5CC34, 0x0FFFCC34, 0x0FFFCCB4,
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| 
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| 	/*
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| 	 * Exception. (Offset 3Ch in UPMA RAM)
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| 	 */
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| 	0x0FEA8C34, 0x1FB54C34, 0xFFFFCC34, _NOT_USED_
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| };
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| 
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| /*
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|  * Check Board Identity:
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|  */
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| 
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| int checkboard (void)
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| {
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| 	puts ("Board: RMU\n") ;
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| 	return (0) ;
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| }
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| long int initdram (int board_type)
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| {
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| 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
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| 	volatile memctl8xx_t *memctl = &immap->im_memctl;
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| 	long int size9;
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| 
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| 	upmconfig (UPMA, (uint *) sdram_table,
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| 		   sizeof (sdram_table) / sizeof (uint));
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| 
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| 	/* Refresh clock prescalar */
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| 	memctl->memc_mptpr = CFG_MPTPR;
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| 
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| 	memctl->memc_mar = 0x00000088;
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| 
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| 	/* Map controller banks 1 to the SDRAM bank */
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| 	memctl->memc_or1 = CFG_OR1_PRELIM;
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| 	memctl->memc_br1 = CFG_BR1_PRELIM;
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| 
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| 	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
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| 
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| 	udelay (200);
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| 
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| 	/* perform SDRAM initializsation sequence */
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| 
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| 	memctl->memc_mcr = 0x80002136;	/* SDRAM bank 0 */
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| 	udelay (1);
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| 
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| 	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
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| 
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| 	udelay (1000);
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| 
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| 	/* Check Bank 0 Memory Size,
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| 	 * 9 column mode
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| 	 */
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| 
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| 	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
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| 			   SDRAM_MAX_SIZE);
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| 
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| 	/*
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| 	 * Final mapping:
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| 	 */
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| 
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| 	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
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| 	udelay (1000);
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| 
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| 	return (size9);
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| }
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| 
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| /* ------------------------------------------------------------------------- */
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| 
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| /*
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|  * Check memory range for valid RAM. A simple memory test determines
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|  * the actually available RAM size between addresses `base' and
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|  * `base + maxsize'. Some (not all) hardware errors are detected:
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|  * - short between address lines
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|  * - short between data lines
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|  */
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| 
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| static long int dram_size (long int mamr_value, long int *base,
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| 			   long int maxsize)
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| {
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| 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
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| 	volatile memctl8xx_t *memctl = &immap->im_memctl;
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| 
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| 	memctl->memc_mamr = mamr_value;
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| 
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| 	return (get_ram_size(base, maxsize));
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| }
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