mirror of
https://github.com/smaeul/u-boot.git
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d04aa29fba
Add DDR3 detection timings for Rockchip RV1126 SoC. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
73 lines
1.8 KiB
PHP
73 lines
1.8 KiB
PHP
{
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{
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{
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.rank = 0x1,
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.col = 0xC,
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.bk = 0x3,
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.bw = 0x0,
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.dbw = 0x0,
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.row_3_4 = 0x0,
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.cs0_row = 0x10,
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.cs1_row = 0x10,
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.cs0_high16bit_row = 0x10,
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.cs1_high16bit_row = 0x10,
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.ddrconfig = 0
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},
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{
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{0x2c0f080e},
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{0x0d030502},
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{0x00000002},
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{0x00001111},
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{0x0000000c},
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{0x00000000},
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0x000000ff
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}
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},
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{
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.ddr_freq = 528, /* clock rate(MHz) */
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.dramtype = DDR3,
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.num_channels = 1,
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.stride = 0,
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.odt = 0
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},
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{
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{
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{0x00000000, 0x43042001}, /* MSTR */
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{0x00000064, 0x0040005d}, /* RFSHTMG */
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{0x000000d0, 0x00020082}, /* INIT0 */
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{0x000000d4, 0x00350000}, /* INIT1 */
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{0x000000d8, 0x00000100}, /* INIT2 */
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{0x000000dc, 0x09400000}, /* INIT3 */
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{0x000000e0, 0x00080000}, /* INIT4 */
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{0x000000e4, 0x00090000}, /* INIT5 */
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{0x000000f4, 0x000f011f}, /* RANKCTL */
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{0x00000100, 0x090e120a}, /* DRAMTMG0 */
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{0x00000104, 0x0007020e}, /* DRAMTMG1 */
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{0x00000108, 0x03040407}, /* DRAMTMG2 */
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{0x0000010c, 0x00202006}, /* DRAMTMG3 */
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{0x00000110, 0x04020305}, /* DRAMTMG4 */
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{0x00000114, 0x03030302}, /* DRAMTMG5 */
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{0x00000120, 0x00000904}, /* DRAMTMG8 */
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{0x00000180, 0x00800020}, /* ZQCTL0 */
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{0x00000184, 0x00000000}, /* ZQCTL1 */
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{0x00000190, 0x07020001}, /* DFITMG0 */
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{0x00000198, 0x07000101}, /* DFILPCFG0 */
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{0x000001a0, 0xc0400003}, /* DFIUPD0 */
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{0x00000240, 0x06000608}, /* ODTCFG */
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{0x00000244, 0x00000201}, /* ODTMAP */
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{0x00000250, 0x00001f00}, /* SCHED */
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{0x00000490, 0x00000001}, /* PCTRL_0 */
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{0xffffffff, 0xffffffff}
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}
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},
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{
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{
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{0x00000004, 0x0000008a}, /* PHYREG01 */
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{0x00000014, 0x00000008}, /* PHYREG05 */
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{0x00000018, 0x00000000}, /* PHYREG06 */
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{0x0000001c, 0x00000006}, /* PHYREG07 */
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{0xffffffff, 0xffffffff}
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}
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}
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},
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