mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-31 20:18:18 +00:00
644e8fc2d5
Add support for ddr4 on rv1126. Timing detection files are imported from downstream Rockchip BSP u-boot. Allow selecting ddr4 ram with define CONFIG_RAM_ROCKCHIP_DDR4. Signed-off-by: Tim Lunn <tim@feathertop.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
76 lines
1.9 KiB
PHP
76 lines
1.9 KiB
PHP
{
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{
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{
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.rank = 0x1,
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.col = 0xA,
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.bk = 0x2,
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.bw = 0x1,
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.dbw = 0x0,
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.row_3_4 = 0x0,
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.cs0_row = 0x11,
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.cs1_row = 0x0,
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.cs0_high16bit_row = 0x11,
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.cs1_high16bit_row = 0x0,
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.ddrconfig = 0
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},
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{
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{0x4d110a0a},
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{0x07020501},
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{0x00000002},
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{0x00001111},
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{0x0000000c},
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{0x00000232},
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0x000000ff
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}
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},
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{
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.ddr_freq = 396, /* clock rate(MHz) */
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.dramtype = DDR4,
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.num_channels = 1,
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.stride = 0,
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.odt = 0
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},
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{
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{
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{0x00000000, 0x43049010}, /* MSTR */
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{0x00000064, 0x00300046}, /* RFSHTMG */
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{0x000000d0, 0x00020062}, /* INIT0 */
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{0x000000d4, 0x00280000}, /* INIT1 */
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{0x000000d8, 0x00000100}, /* INIT2 */
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{0x000000dc, 0x00040000}, /* INIT3 */
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{0x000000e0, 0x00000000}, /* INIT4 */
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{0x000000e4, 0x00110000}, /* INIT5 */
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{0x000000e8, 0x00000420}, /* INIT6 */
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{0x000000ec, 0x00000400}, /* INIT7 */
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{0x000000f4, 0x000f011f}, /* RANKCTL */
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{0x00000100, 0x09070d07}, /* DRAMTMG0 */
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{0x00000104, 0x0002020a}, /* DRAMTMG1 */
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{0x00000108, 0x0505040a}, /* DRAMTMG2 */
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{0x0000010c, 0x0040400c}, /* DRAMTMG3 */
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{0x00000110, 0x05030206}, /* DRAMTMG4 */
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{0x00000114, 0x03030202}, /* DRAMTMG5 */
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{0x00000120, 0x04040b04}, /* DRAMTMG8 */
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{0x00000124, 0x00020208}, /* DRAMTMG9 */
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{0x00000180, 0x01000040}, /* ZQCTL0 */
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{0x00000184, 0x00000000}, /* ZQCTL1 */
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{0x00000190, 0x07030003}, /* DFITMG0 */
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{0x00000198, 0x07000101}, /* DFILPCFG0 */
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{0x000001a0, 0xc0400003}, /* DFIUPD0 */
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{0x00000240, 0x06000604}, /* ODTCFG */
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{0x00000244, 0x00000201}, /* ODTMAP */
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{0x00000250, 0x00001f00}, /* SCHED */
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{0x00000490, 0x00000001}, /* PCTRL_0 */
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{0xffffffff, 0xffffffff}
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}
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},
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{
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{
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{0x00000004, 0x0000008c}, /* PHYREG01 */
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{0x00000014, 0x0000000a}, /* PHYREG05 */
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{0x00000018, 0x00000000}, /* PHYREG06 */
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{0x0000001c, 0x00000009}, /* PHYREG07 */
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{0xffffffff, 0xffffffff}
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}
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}
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},
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