mirror of
https://github.com/smaeul/u-boot.git
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0900840b46
Add LPDDR4 detection timings and support for RV1126. Signed-off-by: Jagan Teki <jagan@edgeble.ai> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
79 lines
2.0 KiB
PHP
79 lines
2.0 KiB
PHP
{
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{
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{
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.rank = 0x1,
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.col = 0xB,
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.bk = 0x3,
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.bw = 0x1,
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.dbw = 0x1,
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.row_3_4 = 0x0,
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.cs0_row = 0x11,
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.cs1_row = 0x11,
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.cs0_high16bit_row = 0x0,
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.cs1_high16bit_row = 0x0,
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.ddrconfig = 0
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},
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{
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{0x2f0d060a},
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{0x07020804},
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{0x00000602},
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{0x00001111},
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{0x00000054},
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{0x00000000},
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0x000000ff
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}
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},
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{
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.ddr_freq = 328, /* clock rate(MHz) */
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.dramtype = LPDDR4,
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.num_channels = 1,
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.stride = 0,
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.odt = 0
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},
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{
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{
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{0x00000000, 0x81081020}, /* MSTR */
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{0x00000064, 0x0014002e}, /* RFSHTMG */
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{0x000000d0, 0x00020142}, /* INIT0 */
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{0x000000d4, 0x00220000}, /* INIT1 */
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{0x000000d8, 0x00000202}, /* INIT2 */
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{0x000000dc, 0x00240012}, /* INIT3 */
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{0x000000e0, 0x00310000}, /* INIT4 */
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{0x000000e8, 0x00100000}, /* INIT6 */
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{0x000000ec, 0x00000000}, /* INIT7 */
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{0x000000f4, 0x000f033f}, /* RANKCTL */
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{0x00000100, 0x0c070507}, /* DRAMTMG0 */
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{0x00000104, 0x0003040b}, /* DRAMTMG1 */
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{0x00000108, 0x04070c0d}, /* DRAMTMG2 */
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{0x0000010c, 0x00505000}, /* DRAMTMG3 */
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{0x00000110, 0x03040204}, /* DRAMTMG4 */
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{0x00000114, 0x02030303}, /* DRAMTMG5 */
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{0x00000118, 0x01010004}, /* DRAMTMG6 */
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{0x0000011c, 0x00000301}, /* DRAMTMG7 */
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{0x00000120, 0x00000303}, /* DRAMTMG8 */
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{0x00000130, 0x00020000}, /* DRAMTMG12 */
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{0x00000134, 0x00100002}, /* DRAMTMG13 */
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{0x00000138, 0x00000030}, /* DRAMTMG14 */
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{0x00000180, 0x00a40005}, /* ZQCTL0 */
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{0x00000184, 0x00900000}, /* ZQCTL1 */
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{0x00000190, 0x07040000}, /* DFITMG0 */
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{0x00000198, 0x07000101}, /* DFILPCFG0 */
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{0x000001a0, 0xc0400003}, /* DFIUPD0 */
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{0x00000240, 0x0905092c}, /* ODTCFG */
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{0x00000244, 0x00000101}, /* ODTMAP */
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{0x00000250, 0x00001f00}, /* SCHED */
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{0x00000490, 0x00000001}, /* PCTRL_0 */
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{0xffffffff, 0xffffffff}
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}
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},
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{
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{
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{0x00000004, 0x0000008d}, /* PHYREG01 */
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{0x00000014, 0x0000000e}, /* PHYREG05 */
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{0x00000018, 0x00000000}, /* PHYREG06 */
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{0x0000001c, 0x00000008}, /* PHYREG07 */
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{0xffffffff, 0xffffffff}
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}
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}
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},
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