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	Add support for AMD Versal Gen 2. SoC is based on Cortex-a78ae 4 cluster/2 cpu core each. A lot of IPs are shared with previous families. There are couple of new IP blocks where the most interesting from user point of view is UFS. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/bc2b70831ce1031bd0fac32357bff84936e1310f.1716994063.git.michal.simek@amd.com
		
			
				
	
	
		
			344 lines
		
	
	
		
			7.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			344 lines
		
	
	
		
			7.0 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0
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| /*
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|  * Copyright (C) 2021 - 2022, Xilinx, Inc.
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|  * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc.
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|  *
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|  * Michal Simek <michal.simek@amd.com>
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|  */
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| 
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| #include <cpu_func.h>
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| #include <fdtdec.h>
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| #include <init.h>
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| #include <env_internal.h>
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| #include <log.h>
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| #include <malloc.h>
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| #include <time.h>
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| #include <asm/cache.h>
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| #include <asm/global_data.h>
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| #include <asm/io.h>
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| #include <asm/arch/hardware.h>
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| #include <asm/arch/sys_proto.h>
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| #include <dm/device.h>
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| #include <dm/uclass.h>
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| #include "../../xilinx/common/board.h"
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| 
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| #include <linux/bitfield.h>
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| #include <debug_uart.h>
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| #include <generated/dt.h>
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| 
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| DECLARE_GLOBAL_DATA_PTR;
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| 
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| int board_init(void)
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| {
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| 	printf("EL Level:\tEL%d\n", current_el());
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| 
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| 	return 0;
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| }
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| 
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| static u32 platform_id, platform_version;
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| 
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| char *soc_name_decode(void)
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| {
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| 	char *name, *platform_name;
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| 
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| 	switch (platform_id) {
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| 	case VERSAL2_SPP:
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| 		platform_name = "spp";
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| 		break;
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| 	case VERSAL2_EMU:
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| 		platform_name = "emu";
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| 		break;
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| 	case VERSAL2_SPP_MMD:
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| 		platform_name = "spp-mmd";
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| 		break;
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| 	case VERSAL2_EMU_MMD:
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| 		platform_name = "emu-mmd";
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| 		break;
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| 	case VERSAL2_QEMU:
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| 		platform_name = "qemu";
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| 		break;
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| 	default:
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| 		return NULL;
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| 	}
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| 
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| 	/*
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| 	 * --rev. are 6 chars
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| 	 * max platform name is qemu which is 4 chars
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| 	 * platform version number are 1+1
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| 	 * Plus 1 char for \n
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| 	 */
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| 	name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13);
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| 	if (!name)
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| 		return NULL;
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| 
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| 	sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD,
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| 		platform_name, platform_version / 10,
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| 		platform_version % 10, current_el());
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| 
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| 	return name;
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| }
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| 
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| bool soc_detection(void)
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| {
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| 	u32 version, ps_version;
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| 
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| 	version = readl(PMC_TAP_VERSION);
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| 	platform_id = FIELD_GET(PLATFORM_MASK, version);
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| 	ps_version = FIELD_GET(PS_VERSION_MASK, version);
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| 
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| 	debug("idcode %x, version %x, usercode %x\n",
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| 	      readl(PMC_TAP_IDCODE), version,
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| 	      readl(PMC_TAP_USERCODE));
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| 
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| 	debug("pmc_ver %lx, ps version %x, rtl version %lx\n",
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| 	      FIELD_GET(PMC_VERSION_MASK, version),
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| 	      ps_version,
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| 	      FIELD_GET(RTL_VERSION_MASK, version));
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| 
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| 	platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version);
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| 
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| 	debug("Platform id: %d version: %d.%d\n", platform_id,
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| 	      platform_version / 10, platform_version % 10);
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| 
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| 	return true;
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| }
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| 
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| int board_early_init_r(void)
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| {
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| 	u32 val;
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| 
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| 	if (current_el() != 3)
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| 		return 0;
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| 
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| 	debug("iou_switch ctrl div0 %x\n",
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| 	      readl(&crlapb_base->iou_switch_ctrl));
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| 
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| 	writel(IOU_SWITCH_CTRL_CLKACT_BIT |
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| 	       (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
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| 	       &crlapb_base->iou_switch_ctrl);
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| 
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| 	/* Global timer init - Program time stamp reference clk */
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| 	val = readl(&crlapb_base->timestamp_ref_ctrl);
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| 	val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
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| 	writel(val, &crlapb_base->timestamp_ref_ctrl);
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| 
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| 	debug("ref ctrl 0x%x\n",
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| 	      readl(&crlapb_base->timestamp_ref_ctrl));
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| 
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| 	/* Clear reset of timestamp reg */
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| 	writel(0, &crlapb_base->rst_timestamp);
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| 
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| 	/*
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| 	 * Program freq register in System counter and
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| 	 * enable system counter.
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| 	 */
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| 	writel(CONFIG_COUNTER_FREQUENCY,
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| 	       &iou_scntr_secure->base_frequency_id_register);
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| 
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| 	debug("counter val 0x%x\n",
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| 	      readl(&iou_scntr_secure->base_frequency_id_register));
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| 
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| 	writel(IOU_SCNTRS_CONTROL_EN,
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| 	       &iou_scntr_secure->counter_control_register);
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| 
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| 	debug("scntrs control 0x%x\n",
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| 	      readl(&iou_scntr_secure->counter_control_register));
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| 	debug("timer 0x%llx\n", get_ticks());
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| 	debug("timer 0x%llx\n", get_ticks());
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| 
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| 	return 0;
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| }
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| 
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| static u8 versal_net_get_bootmode(void)
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| {
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| 	u8 bootmode;
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| 	u32 reg = 0;
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| 
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| 	reg = readl(&crp_base->boot_mode_usr);
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| 
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| 	if (reg >> BOOT_MODE_ALT_SHIFT)
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| 		reg >>= BOOT_MODE_ALT_SHIFT;
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| 
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| 	bootmode = reg & BOOT_MODES_MASK;
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| 
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| 	return bootmode;
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| }
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| 
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| static int boot_targets_setup(void)
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| {
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| 	u8 bootmode;
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| 	struct udevice *dev;
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| 	int bootseq = -1;
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| 	int bootseq_len = 0;
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| 	int env_targets_len = 0;
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| 	const char *mode = NULL;
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| 	char *new_targets;
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| 	char *env_targets;
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| 
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| 	bootmode = versal_net_get_bootmode();
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| 
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| 	puts("Bootmode: ");
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| 	switch (bootmode) {
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| 	case USB_MODE:
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| 		puts("USB_MODE\n");
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| 		mode = "usb_dfu0 usb_dfu1";
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| 		break;
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| 	case JTAG_MODE:
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| 		puts("JTAG_MODE\n");
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| 		mode = "jtag pxe dhcp";
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| 		break;
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| 	case QSPI_MODE_24BIT:
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| 		puts("QSPI_MODE_24\n");
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| 		if (uclass_get_device_by_name(UCLASS_SPI,
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| 					      "spi@f1030000", &dev)) {
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| 			debug("QSPI driver for QSPI device is not present\n");
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| 			break;
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| 		}
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| 		mode = "xspi";
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| 		bootseq = dev_seq(dev);
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| 		break;
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| 	case QSPI_MODE_32BIT:
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| 		puts("QSPI_MODE_32\n");
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| 		if (uclass_get_device_by_name(UCLASS_SPI,
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| 					      "spi@f1030000", &dev)) {
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| 			debug("QSPI driver for QSPI device is not present\n");
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| 			break;
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| 		}
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| 		mode = "xspi";
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| 		bootseq = dev_seq(dev);
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| 		break;
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| 	case OSPI_MODE:
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| 		puts("OSPI_MODE\n");
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| 		if (uclass_get_device_by_name(UCLASS_SPI,
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| 					      "spi@f1010000", &dev)) {
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| 			debug("OSPI driver for OSPI device is not present\n");
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| 			break;
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| 		}
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| 		mode = "xspi";
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| 		bootseq = dev_seq(dev);
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| 		break;
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| 	case EMMC_MODE:
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| 		puts("EMMC_MODE\n");
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| 		mode = "mmc";
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| 		bootseq = dev_seq(dev);
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| 		break;
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| 	case SELECTMAP_MODE:
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| 		puts("SELECTMAP_MODE\n");
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| 		break;
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| 	case SD_MODE:
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| 		puts("SD_MODE\n");
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| 		if (uclass_get_device_by_name(UCLASS_MMC,
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| 					      "mmc@f1040000", &dev)) {
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| 			debug("SD0 driver for SD0 device is not present\n");
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| 			break;
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| 		}
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| 		debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
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| 
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| 		mode = "mmc";
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| 		bootseq = dev_seq(dev);
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| 		break;
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| 	case SD1_LSHFT_MODE:
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| 		puts("LVL_SHFT_");
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| 		fallthrough;
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| 	case SD_MODE1:
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| 		puts("SD_MODE1\n");
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| 		if (uclass_get_device_by_name(UCLASS_MMC,
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| 					      "mmc@f1050000", &dev)) {
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| 			debug("SD1 driver for SD1 device is not present\n");
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| 			break;
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| 		}
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| 		debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
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| 
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| 		mode = "mmc";
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| 		bootseq = dev_seq(dev);
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| 		break;
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| 	default:
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| 		printf("Invalid Boot Mode:0x%x\n", bootmode);
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| 		break;
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| 	}
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| 
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| 	if (mode) {
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| 		if (bootseq >= 0) {
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| 			bootseq_len = snprintf(NULL, 0, "%i", bootseq);
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| 			debug("Bootseq len: %x\n", bootseq_len);
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| 		}
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| 
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| 		/*
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| 		 * One terminating char + one byte for space between mode
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| 		 * and default boot_targets
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| 		 */
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| 		env_targets = env_get("boot_targets");
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| 		if (env_targets)
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| 			env_targets_len = strlen(env_targets);
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| 
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| 		new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
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| 				     bootseq_len);
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| 		if (!new_targets)
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| 			return -ENOMEM;
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| 
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| 		if (bootseq >= 0)
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| 			sprintf(new_targets, "%s%x %s", mode, bootseq,
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| 				env_targets ? env_targets : "");
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| 		else
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| 			sprintf(new_targets, "%s %s", mode,
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| 				env_targets ? env_targets : "");
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| 
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| 		env_set("boot_targets", new_targets);
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| 	}
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| 
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| 	return 0;
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| }
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| 
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| int board_late_init(void)
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| {
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| 	int ret;
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| 
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| 	if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
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| 		debug("Saved variables - Skipping\n");
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| 		return 0;
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| 	}
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| 
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| 	if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG))
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| 		return 0;
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| 
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| 	if (IS_ENABLED(CONFIG_DISTRO_DEFAULTS)) {
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| 		ret = boot_targets_setup();
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| 		if (ret)
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| 			return ret;
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| 	}
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| 
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| 	return board_late_init_xilinx();
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| }
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| 
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| int dram_init_banksize(void)
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| {
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| 	int ret;
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| 
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| 	ret = fdtdec_setup_memory_banksize();
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| 	if (ret)
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| 		return ret;
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| 
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| 	mem_map_fill();
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| 
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| 	return 0;
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| }
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| 
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| int dram_init(void)
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| {
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| 	int ret;
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| 
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| 	if (IS_ENABLED(CONFIG_SYS_MEM_RSVD_FOR_MMU))
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| 		ret = fdtdec_setup_mem_size_base();
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| 	else
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| 		ret = fdtdec_setup_mem_size_base_lowest();
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| 
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| 	if (ret)
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| 		return -EINVAL;
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| 
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| 	return 0;
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| }
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| 
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| void reset_cpu(void)
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| {
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| }
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