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174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
18 lines
346 B
C
18 lines
346 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2019 Xilinx, Inc,
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* Siva Durga Prasad Paladugu <siva.durga.prasad.paladugu@amd.com>>
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*/
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#ifndef _VERSALPL_H_
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#define _VERSALPL_H_
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#include <xilinx.h>
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#define VERSAL_PM_LOAD_PDI 0x701
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#define VERSAL_PM_PDI_TYPE 0xF
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extern struct xilinx_fpga_op versal_op;
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#endif /* _VERSALPL_H_ */
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