mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-04 05:50:17 +00:00
feb64f9d51
Fix warning below: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
844 lines
18 KiB
Plaintext
844 lines
18 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Google Veyron (and derivatives) board device tree source
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*
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* Copyright 2014 Google, Inc
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*/
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#include <dt-bindings/clock/rockchip,rk808.h>
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#include <dt-bindings/input/input.h>
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#include "rk3288.dtsi"
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/ {
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memory {
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reg = <0x0 0x80000000>;
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};
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chosen {
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stdout-path = &uart2;
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};
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config {
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u-boot,dm-pre-reloc;
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u-boot,boot0 = &spi_flash;
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};
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firmware {
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chromeos {
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pinctrl-names = "default";
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pinctrl-0 = <&fw_wp_ap>;
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write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>;
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};
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};
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backlight: backlight {
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compatible = "pwm-backlight";
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brightness-levels = <
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0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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default-brightness-level = <128>;
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enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
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backlight-boot-off;
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pinctrl-names = "default";
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pinctrl-0 = <&bl_en>;
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pwms = <&pwm0 0 1000000 0>;
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};
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panel: panel {
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compatible ="cnm,n116bgeea2","simple-panel";
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status = "okay";
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power-supply = <&vcc33_lcd>;
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backlight = <&backlight>;
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};
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gpio_keys: gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pwr_key_h>;
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power {
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label = "Power";
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gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_POWER>;
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debounce-interval = <100>;
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gpio-key,wakeup;
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};
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};
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gpio-restart {
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compatible = "gpio-restart";
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gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&ap_warm_reset_h>;
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priority = /bits/ 8 <200>;
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};
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emmc_pwrseq: emmc-pwrseq {
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compatible = "mmc-pwrseq-emmc";
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pinctrl-0 = <&emmc_reset>;
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pinctrl-names = "default";
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reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
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};
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sound {
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compatible = "rockchip,rockchip-audio-max98090";
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rockchip,model = "ROCKCHIP-I2S";
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rockchip,i2s-controller = <&i2s>;
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rockchip,audio-codec = <&max98090>;
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rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
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rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
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rockchip,headset-codec = <&headsetcodec>;
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pinctrl-names = "default";
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pinctrl-0 = <&mic_det>, <&hp_det>;
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};
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vdd_logic: pwm-regulator {
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compatible = "pwm-regulator";
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pwms = <&pwm1 0 2000 0>;
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voltage-table = <1350000 0>,
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<1300000 10>,
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<1250000 20>,
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<1200000 31>,
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<1150000 41>,
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<1100000 52>,
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<1050000 62>,
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<1000000 72>,
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< 950000 83>;
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regulator-min-microvolt = <950000>;
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regulator-max-microvolt = <1350000>;
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regulator-name = "vdd_logic";
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regulator-ramp-delay = <4000>;
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};
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vcc33_sys: vcc33-sys {
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compatible = "regulator-fixed";
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regulator-name = "vcc33_sys";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vccsys>;
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};
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vcc_5v: vcc-5v {
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compatible = "regulator-fixed";
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regulator-name = "vcc_5v";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vcc50_hdmi: vcc50-hdmi {
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compatible = "regulator-fixed";
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regulator-name = "vcc50_hdmi";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc_5v>;
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};
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bt_regulator: bt-regulator {
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/*
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* On the module itself this is one of these (depending
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* on the actual card pouplated):
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* - BT_I2S_WS_BT_RFDISABLE_L
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* - No connect
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*/
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&bt_enable_l>;
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regulator-name = "bt_regulator";
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};
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wifi_regulator: wifi-regulator {
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/*
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* On the module itself this is one of these (depending
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* on the actual card populated):
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* - SDIO_RESET_L_WL_REG_ON
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* - PDN (power down when low)
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*/
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compatible = "regulator-fixed";
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enable-active-high;
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gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_enable_h>;
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regulator-name = "wifi_regulator";
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/* Faux input supply. See bt_regulator description. */
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vin-supply = <&bt_regulator>;
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};
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io-domains {
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compatible = "rockchip,rk3288-io-voltage-domain";
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rockchip,grf = <&grf>;
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audio-supply = <&vcc18_codec>;
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bb-supply = <&vcc33_io>;
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dvp-supply = <&vcc_18>;
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flash0-supply = <&vcc18_flashio>;
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gpio1830-supply = <&vcc33_io>;
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gpio30-supply = <&vcc33_io>;
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lcdc-supply = <&vcc33_lcd>;
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sdcard-supply = <&vccio_sd>;
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wifi-supply = <&vcc18_wl>;
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};
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};
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&cpu0 {
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cpu0-supply = <&vdd_cpu>;
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};
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&dmc {
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logic-supply = <&vdd_logic>;
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rockchip,odt-disable-freq = <333000000>;
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rockchip,dll-disable-freq = <333000000>;
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rockchip,sr-enable-freq = <333000000>;
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rockchip,pd-enable-freq = <666000000>;
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rockchip,auto-self-refresh-cnt = <0>;
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rockchip,auto-power-down-cnt = <64>;
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rockchip,ddr-speed-bin = <21>;
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rockchip,trcd = <10>;
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rockchip,trp = <10>;
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operating-points = <
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/* KHz uV */
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200000 1050000
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333000 1100000
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533000 1150000
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666000 1200000
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>;
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};
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&efuse {
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status = "okay";
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};
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&emmc {
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broken-cd;
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bus-width = <8>;
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cap-mmc-highspeed;
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mmc-hs200-1_8v;
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mmc-pwrseq = <&emmc_pwrseq>;
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disable-wp;
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non-removable;
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num-slots = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>;
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status = "okay";
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};
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&sdio0 {
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broken-cd;
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bus-width = <4>;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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cap-sdio-irq;
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card-external-vcc-supply = <&wifi_regulator>;
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clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>,
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<&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock";
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keep-power-in-suspend;
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non-removable;
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num-slots = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>;
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status = "okay";
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vmmc-supply = <&vcc33_sys>;
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vqmmc-supply = <&vcc18_wl>;
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};
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&sdmmc {
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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card-detect-delay = <200>;
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cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
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num-slots = <1>;
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status = "okay";
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vmmc-supply = <&vcc33_sd>;
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vqmmc-supply = <&vccio_sd>;
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};
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&spi2 {
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status = "okay";
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u-boot,dm-pre-reloc;
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spi_flash: spiflash@0 {
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u-boot,dm-pre-reloc;
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compatible = "spidev", "spi-flash";
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spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */
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reg = <0>;
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};
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};
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&i2c0 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
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i2c-scl-rising-time-ns = <100>; /* 45ns measured */
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u-boot,dm-pre-reloc;
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rk808: pmic@1b {
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compatible = "rockchip,rk808";
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clock-output-names = "xin32k", "wifibt_32kin";
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interrupt-parent = <&gpio0>;
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l>;
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reg = <0x1b>;
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rockchip,system-power-controller;
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wakeup-source;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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vcc1-supply = <&vcc33_sys>;
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vcc2-supply = <&vcc33_sys>;
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vcc3-supply = <&vcc33_sys>;
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vcc4-supply = <&vcc33_sys>;
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vcc6-supply = <&vcc_5v>;
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vcc7-supply = <&vcc33_sys>;
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vcc8-supply = <&vcc33_sys>;
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vcc9-supply = <&vcc_5v>;
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vcc10-supply = <&vcc33_sys>;
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vcc11-supply = <&vcc_5v>;
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vcc12-supply = <&vcc_18>;
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vddio-supply = <&vcc33_io>;
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regulators {
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vdd_cpu: DCDC_REG1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <1450000>;
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regulator-name = "vdd_arm";
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regulator-ramp-delay = <6001>;
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regulator-suspend-mem-disabled;
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};
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vdd_gpu: DCDC_REG2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1250000>;
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regulator-name = "vdd_gpu";
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regulator-ramp-delay = <6001>;
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regulator-suspend-mem-disabled;
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};
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vcc135_ddr: DCDC_REG3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vcc135_ddr";
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regulator-suspend-mem-enabled;
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};
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/*
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* vcc_18 has several aliases. (vcc18_flashio and
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* vcc18_wl). We'll add those aliases here just to
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* make it easier to follow the schematic. The signals
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* are actually hooked together and only separated for
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* power measurement purposes).
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*/
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vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcc_18";
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regulator-suspend-mem-microvolt = <1800000>;
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};
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/*
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* Note that both vcc33_io and vcc33_pmuio are always
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* powered together. To simplify the logic in the dts
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* we just refer to vcc33_io every time something is
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* powered from vcc33_pmuio. In fact, on later boards
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* (such as danger) they're the same net.
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*/
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vcc33_io: LDO_REG1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc33_io";
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regulator-suspend-mem-microvolt = <3300000>;
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};
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vdd_10: LDO_REG3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-name = "vdd_10";
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regulator-suspend-mem-microvolt = <1000000>;
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};
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vccio_sd: LDO_REG4 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vccio_sd";
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regulator-suspend-mem-disabled;
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};
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vcc33_sd: LDO_REG5 {
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc33_sd";
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regulator-suspend-mem-disabled;
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};
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vcc18_codec: LDO_REG6 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcc18_codec";
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regulator-suspend-mem-disabled;
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};
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vdd10_lcd_pwren_h: LDO_REG7 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-name = "vdd10_lcd_pwren_h";
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regulator-suspend-mem-disabled;
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};
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vcc33_lcd: SWITCH_REG1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vcc33_lcd";
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regulator-suspend-mem-disabled;
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};
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};
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};
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */
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i2c-scl-rising-time-ns = <100>; /* 40ns measured */
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tpm: tpm@20 {
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compatible = "infineon,slb9645tt";
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reg = <0x20>;
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powered-while-suspended;
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};
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};
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&i2c2 {
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status = "okay";
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/* 100kHz since 4.7k resistors don't rise fast enough */
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clock-frequency = <100000>;
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i2c-scl-falling-time-ns = <50>; /* 10ns measured */
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i2c-scl-rising-time-ns = <800>; /* 600ns measured */
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max98090: max98090@10 {
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compatible = "maxim,max98090";
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reg = <0x10>;
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interrupt-parent = <&gpio6>;
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interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
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pinctrl-names = "default";
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pinctrl-0 = <&int_codec>;
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};
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};
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&i2c3 {
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status = "okay";
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clock-frequency = <400000>;
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i2c-scl-falling-time-ns = <50>;
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i2c-scl-rising-time-ns = <300>;
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};
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&i2c4 {
|
|
status = "okay";
|
|
|
|
clock-frequency = <400000>;
|
|
i2c-scl-falling-time-ns = <50>; /* 11ns measured */
|
|
i2c-scl-rising-time-ns = <300>; /* 225ns measured */
|
|
|
|
headsetcodec: ts3a227e@3b {
|
|
compatible = "ti,ts3a227e";
|
|
reg = <0x3b>;
|
|
interrupt-parent = <&gpio0>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&ts3a227e_int_l>;
|
|
ti,micbias = <7>; /* MICBIAS = 2.8V */
|
|
};
|
|
};
|
|
|
|
&i2c5 {
|
|
status = "okay";
|
|
|
|
clock-frequency = <100000>;
|
|
i2c-scl-falling-time-ns = <300>;
|
|
i2c-scl-rising-time-ns = <1000>;
|
|
};
|
|
|
|
&i2s {
|
|
status = "okay";
|
|
clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
|
|
clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
|
|
};
|
|
|
|
&wdt {
|
|
status = "okay";
|
|
};
|
|
|
|
&pwm0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&pwm1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
|
|
/* Pins don't include flow control by default; add that in */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
|
/* We need to go faster than 24MHz, so adjust clock parents / rates */
|
|
assigned-clocks = <&cru SCLK_UART0>;
|
|
assigned-clock-rates = <48000000>;
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart2 {
|
|
status = "okay";
|
|
u-boot,dm-pre-reloc;
|
|
reg-shift = <2>;
|
|
};
|
|
|
|
&vopb {
|
|
status = "okay";
|
|
};
|
|
|
|
&vopb_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&vopl {
|
|
status = "okay";
|
|
};
|
|
|
|
&vopl_mmu {
|
|
status = "okay";
|
|
};
|
|
|
|
&edp {
|
|
status = "okay";
|
|
rockchip,panel = <&panel>;
|
|
};
|
|
|
|
&hdmi {
|
|
status = "okay";
|
|
};
|
|
|
|
&hdmi_audio {
|
|
status = "okay";
|
|
};
|
|
|
|
&gpu {
|
|
status = "okay";
|
|
};
|
|
|
|
&tsadc {
|
|
tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
|
|
tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
|
|
status = "okay";
|
|
};
|
|
|
|
&pinctrl {
|
|
u-boot,dm-pre-reloc;
|
|
pinctrl-names = "default", "sleep";
|
|
pinctrl-0 = <
|
|
/* Common for sleep and wake, but no owners */
|
|
&ddr0_retention
|
|
&ddrio_pwroff
|
|
&global_pwroff
|
|
|
|
/* Wake only */
|
|
&bt_dev_wake_awake
|
|
>;
|
|
pinctrl-1 = <
|
|
/* Common for sleep and wake, but no owners */
|
|
&ddr0_retention
|
|
&ddrio_pwroff
|
|
&global_pwroff
|
|
|
|
/* Sleep only */
|
|
&bt_dev_wake_sleep
|
|
>;
|
|
|
|
/* Add this for sdmmc pins to SD card */
|
|
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
|
|
bias-pull-up;
|
|
drive-strength = <8>;
|
|
};
|
|
|
|
pcfg_output_high: pcfg-output-high {
|
|
output-high;
|
|
};
|
|
|
|
pcfg_output_low: pcfg-output-low {
|
|
output-low;
|
|
};
|
|
|
|
backlight {
|
|
bl_en: bl-en {
|
|
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
buttons {
|
|
pwr_key_h: pwr-key-h {
|
|
rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
codec {
|
|
hp_det: hp-det {
|
|
rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
int_codec: int-codec {
|
|
rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
mic_det: mic-det {
|
|
rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
emmc {
|
|
emmc_reset: emmc-reset {
|
|
rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
/*
|
|
* We run eMMC at max speed; bump up drive strength.
|
|
* We also have external pulls, so disable the internal ones.
|
|
*/
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
|
<3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
|
<3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
|
<3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
|
<3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
|
<3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
|
<3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>,
|
|
<3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
};
|
|
|
|
headset {
|
|
ts3a227e_int_l: ts3a227e-int-l {
|
|
rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
};
|
|
};
|
|
|
|
pmic {
|
|
pmic_int_l: pmic-int-l {
|
|
/*
|
|
* Causes jerry to hang when probing bus 0
|
|
* rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
|
|
*/
|
|
};
|
|
};
|
|
|
|
reboot {
|
|
ap_warm_reset_h: ap-warm-reset-h {
|
|
rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
sdio0 {
|
|
wifi_enable_h: wifienable-h {
|
|
rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
/* NOTE: mislabelled on schematic; should be bt_enable_h */
|
|
bt_enable_l: bt-enable-l {
|
|
rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
/*
|
|
* We run sdio0 at max speed; bump up drive strength.
|
|
* We also have external pulls, so disable the internal ones.
|
|
*/
|
|
sdio0_bus4: sdio0-bus4 {
|
|
rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
|
<4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
|
<4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
|
<4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
sdio0_cmd: sdio0-cmd {
|
|
rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
sdio0_clk: sdio0-clk {
|
|
rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
/*
|
|
* These pins are only present on very new veyron boards; on
|
|
* older boards bt_dev_wake is simply always high. Note that
|
|
* gpio4_26 is a NC on old veyron boards, so it doesn't hurt
|
|
* to map this pin everywhere
|
|
*/
|
|
bt_dev_wake_sleep: bt-dev-wake-sleep {
|
|
rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>;
|
|
};
|
|
|
|
bt_dev_wake_awake: bt-dev-wake-awake {
|
|
rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>;
|
|
};
|
|
};
|
|
|
|
sdmmc {
|
|
/*
|
|
* We run sdmmc at max speed; bump up drive strength.
|
|
* We also have external pulls, so disable the internal ones.
|
|
*/
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
|
<6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
|
<6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>,
|
|
<6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
|
|
};
|
|
|
|
/*
|
|
* Builtin CD line is hooked to ground to prevent JTAG at boot
|
|
* (and also to get the voltage rail correct). Make we
|
|
* configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't
|
|
* think there's a card inserted
|
|
*/
|
|
sdmmc_cd_disabled: sdmmc-cd-disabled {
|
|
rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
/* This is where we actually hook up CD */
|
|
sdmmc_cd_gpio: sdmmc-cd-gpio {
|
|
rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
tpm {
|
|
tpm_int_h: tpm-int-h {
|
|
rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
write-protect {
|
|
fw_wp_ap: fw-wp-ap {
|
|
rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&usbphy {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_host0_ehci {
|
|
status = "okay";
|
|
needs-reset-on-resume;
|
|
};
|
|
|
|
&usb_host1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_otg {
|
|
dr_mode = "host";
|
|
status = "okay";
|
|
assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
|
|
assigned-clock-parents = <&cru SCLK_OTGPHY0>;
|
|
};
|
|
|
|
&sdmmc {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpio3 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpio8 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|