mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-04 05:50:17 +00:00
1d60f2b986
Switch to generic board so that this board will not be broken/removed. Signed-off-by: Simon Glass <sjg@chromium.org>
549 lines
14 KiB
C
549 lines
14 KiB
C
/*
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* (C) Copyright 2000-2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/ppc4xx-emac.h>
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#include <asm/processor.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/ppc4xx.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_SYS_PLL_RECONFIG
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#define CONFIG_SYS_PLL_RECONFIG 0
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#endif
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#if defined(CONFIG_440EPX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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static void reset_with_rli(void)
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{
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u32 reg;
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/*
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* Set reload inhibit so configuration will persist across
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* processor resets
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*/
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mfcpr(CPR0_ICFG, reg);
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reg |= CPR0_ICFG_RLI_MASK;
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mtcpr(CPR0_ICFG, reg);
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/* Reset processor if configuration changed */
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__asm__ __volatile__ ("sync; isync");
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mtspr(SPRN_DBCR0, 0x20000000);
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}
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#endif
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void reconfigure_pll(u32 new_cpu_freq)
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{
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#if defined(CONFIG_440EPX)
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int reset_needed = 0;
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u32 reg, temp;
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u32 prbdv0, target_prbdv0, /* CLK_PRIMBD */
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fwdva, target_fwdva, fwdvb, target_fwdvb, /* CLK_PLLD */
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fbdv, target_fbdv, lfbdv, target_lfbdv,
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perdv0, target_perdv0, /* CLK_PERD */
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spcid0, target_spcid0; /* CLK_SPCID */
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/* Reconfigure clocks if necessary.
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* See PPC440EPx User's Manual, sections 8.2 and 14 */
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if (new_cpu_freq == 667) {
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target_prbdv0 = 2;
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target_fwdva = 2;
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target_fwdvb = 4;
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target_fbdv = 20;
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target_lfbdv = 1;
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target_perdv0 = 4;
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target_spcid0 = 4;
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mfcpr(CPR0_PRIMBD0, reg);
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temp = (reg & PRBDV_MASK) >> 24;
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prbdv0 = temp ? temp : 8;
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if (prbdv0 != target_prbdv0) {
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reg &= ~PRBDV_MASK;
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reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24);
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mtcpr(CPR0_PRIMBD0, reg);
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reset_needed = 1;
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}
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mfcpr(CPR0_PLLD, reg);
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temp = (reg & PLLD_FWDVA_MASK) >> 16;
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fwdva = temp ? temp : 16;
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temp = (reg & PLLD_FWDVB_MASK) >> 8;
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fwdvb = temp ? temp : 8;
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temp = (reg & PLLD_FBDV_MASK) >> 24;
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fbdv = temp ? temp : 32;
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temp = (reg & PLLD_LFBDV_MASK);
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lfbdv = temp ? temp : 64;
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if (fwdva != target_fwdva || fbdv != target_fbdv || lfbdv != target_lfbdv) {
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reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
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PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
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reg |= ((target_fwdva == 16 ? 0 : target_fwdva) << 16) |
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((target_fwdvb == 8 ? 0 : target_fwdvb) << 8) |
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((target_fbdv == 32 ? 0 : target_fbdv) << 24) |
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(target_lfbdv == 64 ? 0 : target_lfbdv);
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mtcpr(CPR0_PLLD, reg);
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reset_needed = 1;
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}
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mfcpr(CPR0_PERD, reg);
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perdv0 = (reg & CPR0_PERD_PERDV0_MASK) >> 24;
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if (perdv0 != target_perdv0) {
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reg &= ~CPR0_PERD_PERDV0_MASK;
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reg |= (target_perdv0 << 24);
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mtcpr(CPR0_PERD, reg);
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reset_needed = 1;
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}
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mfcpr(CPR0_SPCID, reg);
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temp = (reg & CPR0_SPCID_SPCIDV0_MASK) >> 24;
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spcid0 = temp ? temp : 4;
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if (spcid0 != target_spcid0) {
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reg &= ~CPR0_SPCID_SPCIDV0_MASK;
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reg |= ((target_spcid0 == 4 ? 0 : target_spcid0) << 24);
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mtcpr(CPR0_SPCID, reg);
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reset_needed = 1;
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}
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}
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/* Get current value of FWDVA.*/
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mfcpr(CPR0_PLLD, reg);
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temp = (reg & PLLD_FWDVA_MASK) >> 16;
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/*
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* Check to see if FWDVA has been set to value of 1. if it has we must
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* modify it.
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*/
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if (temp == 1) {
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/*
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* Load register that contains current boot strapping option.
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*/
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mfcpr(CPR0_ICFG, reg);
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/*
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* Strapping option bits (ICS) are already in correct position,
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* only masking needed.
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*/
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reg &= CPR0_ICFG_ICS_MASK;
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if ((reg == BOOT_STRAP_OPTION_A) || (reg == BOOT_STRAP_OPTION_B) ||
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(reg == BOOT_STRAP_OPTION_D) || (reg == BOOT_STRAP_OPTION_E)) {
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mfcpr(CPR0_PLLD, reg);
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/* Get current value of fbdv. */
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temp = (reg & PLLD_FBDV_MASK) >> 24;
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fbdv = temp ? temp : 32;
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/* Get current value of lfbdv. */
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temp = (reg & PLLD_LFBDV_MASK);
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lfbdv = temp ? temp : 64;
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/*
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* Get current value of FWDVA. Assign current FWDVA to
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* new FWDVB.
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*/
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mfcpr(CPR0_PLLD, reg);
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target_fwdvb = (reg & PLLD_FWDVA_MASK) >> 16;
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fwdvb = target_fwdvb ? target_fwdvb : 8;
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/*
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* Get current value of FWDVB. Assign current FWDVB to
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* new FWDVA.
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*/
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target_fwdva = (reg & PLLD_FWDVB_MASK) >> 8;
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fwdva = target_fwdva ? target_fwdva : 16;
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/*
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* Update CPR0_PLLD with switched FWDVA and FWDVB.
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*/
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reg &= ~(PLLD_FWDVA_MASK | PLLD_FWDVB_MASK |
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PLLD_FBDV_MASK | PLLD_LFBDV_MASK);
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reg |= ((fwdva == 16 ? 0 : fwdva) << 16) |
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((fwdvb == 8 ? 0 : fwdvb) << 8) |
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((fbdv == 32 ? 0 : fbdv) << 24) |
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(lfbdv == 64 ? 0 : lfbdv);
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mtcpr(CPR0_PLLD, reg);
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/* Acknowledge that a reset is required. */
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reset_needed = 1;
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}
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}
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/* Now reset the CPU if needed */
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if (reset_needed)
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reset_with_rli();
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#endif
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#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
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u32 reg;
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/*
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* See "9.2.1.1 Booting with Option E" in the 460EX/GT
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* users manual
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*/
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mfcpr(CPR0_PLLC, reg);
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if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
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/*
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* Set engage bit
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*/
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reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG;
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mtcpr(CPR0_PLLC, reg);
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/* Now reset the CPU */
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reset_with_rli();
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}
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#endif
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}
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#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
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void
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chip_21_errata(void)
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{
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/*
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* See rev 1.09 of the 405EX/405EXr errata. CHIP_21 says that
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* sometimes reading the PVR and/or SDR0_ECID results in incorrect
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* values. Since the rev-D chip uses the SDR0_ECID bits to control
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* internal features, that means the second PCIe or ethernet of an EX
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* variant could fail to work. Also, security features of both EX and
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* EXr might be incorrectly disabled.
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*
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* The suggested workaround is as follows (covering rev-C and rev-D):
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*
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* 1.Read the PVR and SDR0_ECID3.
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*
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* 2.If the PVR matches an expected Revision C PVR value AND if
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* SDR0_ECID3[12:15] is different from PVR[28:31], then processor is
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* Revision C: continue executing the initialization code (no reset
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* required). else go to step 3.
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*
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* 3.If the PVR matches an expected Revision D PVR value AND if
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* SDR0_ECID3[10:11] matches its expected value, then continue
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* executing initialization code, no reset required. else write
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* DBCR0[RST] = 0b11 to generate a SysReset.
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*/
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u32 pvr;
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u32 pvr_28_31;
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u32 ecid3;
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u32 ecid3_10_11;
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u32 ecid3_12_15;
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/* Step 1: */
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pvr = get_pvr();
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mfsdr(SDR0_ECID3, ecid3);
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/* Step 2: */
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pvr_28_31 = pvr & 0xf;
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ecid3_10_11 = (ecid3 >> 20) & 0x3;
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ecid3_12_15 = (ecid3 >> 16) & 0xf;
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if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_C) &&
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(pvr_28_31 != ecid3_12_15)) {
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/* No reset required. */
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return;
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}
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/* Step 3: */
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if ((pvr == CONFIG_405EX_CHIP21_PVR_REV_D) &&
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(ecid3_10_11 == CONFIG_405EX_CHIP21_ECID3_REV_D)) {
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/* No reset required. */
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return;
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}
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/* Reset required. */
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__asm__ __volatile__ ("sync; isync");
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mtspr(SPRN_DBCR0, 0x30000000);
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}
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#endif
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/*
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* Breath some life into the CPU...
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*
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* Reconfigure PLL if necessary,
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* set up the memory map,
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* initialize a bunch of registers
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*/
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void
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cpu_init_f (void)
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{
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#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
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u32 val;
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#endif
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#ifdef CONFIG_SYS_4xx_CHIP_21_ERRATA
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chip_21_errata();
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#endif
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reconfigure_pll(CONFIG_SYS_PLL_RECONFIG);
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#if (defined(CONFIG_405EP) || defined (CONFIG_405EX)) && \
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!defined(CONFIG_SYS_4xx_GPIO_TABLE)
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/*
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* GPIO0 setup (select GPIO or alternate function)
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*/
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#if defined(CONFIG_SYS_GPIO0_OR)
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out32(GPIO0_OR, CONFIG_SYS_GPIO0_OR); /* set initial state of output pins */
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#endif
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#if defined(CONFIG_SYS_GPIO0_ODR)
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out32(GPIO0_ODR, CONFIG_SYS_GPIO0_ODR); /* open-drain select */
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#endif
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out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH); /* output select */
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out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
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out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H); /* input select */
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out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
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out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH); /* three-state select */
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out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
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#if defined(CONFIG_SYS_GPIO0_ISR2H)
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out32(GPIO0_ISR2H, CONFIG_SYS_GPIO0_ISR2H);
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out32(GPIO0_ISR2L, CONFIG_SYS_GPIO0_ISR2L);
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#endif
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#if defined (CONFIG_SYS_GPIO0_TCR)
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out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR); /* enable output driver for outputs */
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#endif
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#endif /* CONFIG_405EP ... && !CONFIG_SYS_4xx_GPIO_TABLE */
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#if defined (CONFIG_405EP)
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/*
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* Set EMAC noise filter bits
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*/
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mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE);
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#endif /* CONFIG_405EP */
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#if defined(CONFIG_SYS_4xx_GPIO_TABLE)
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gpio_set_chip_configuration();
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#endif /* CONFIG_SYS_4xx_GPIO_TABLE */
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/*
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* External Bus Controller (EBC) Setup
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*/
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#if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
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#if (defined(CONFIG_405GP) || \
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defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
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defined(CONFIG_405EX) || defined(CONFIG_405))
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/*
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* Move the next instructions into icache, since these modify the flash
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* we are running from!
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*/
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asm volatile(" bl 0f" ::: "lr");
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asm volatile("0: mflr 3" ::: "r3");
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asm volatile(" addi 4, 0, 14" ::: "r4");
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asm volatile(" mtctr 4" ::: "ctr");
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asm volatile("1: icbt 0, 3");
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asm volatile(" addi 3, 3, 32" ::: "r3");
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asm volatile(" bdnz 1b" ::: "ctr", "cr0");
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asm volatile(" addis 3, 0, 0x0" ::: "r3");
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asm volatile(" ori 3, 3, 0xA000" ::: "r3");
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asm volatile(" mtctr 3" ::: "ctr");
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asm volatile("2: bdnz 2b" ::: "ctr", "cr0");
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#endif
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mtebc(PB0AP, CONFIG_SYS_EBC_PB0AP);
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mtebc(PB0CR, CONFIG_SYS_EBC_PB0CR);
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#endif
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#if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 1))
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mtebc(PB1AP, CONFIG_SYS_EBC_PB1AP);
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mtebc(PB1CR, CONFIG_SYS_EBC_PB1CR);
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#endif
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#if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 2))
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mtebc(PB2AP, CONFIG_SYS_EBC_PB2AP);
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mtebc(PB2CR, CONFIG_SYS_EBC_PB2CR);
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#endif
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#if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 3))
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mtebc(PB3AP, CONFIG_SYS_EBC_PB3AP);
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mtebc(PB3CR, CONFIG_SYS_EBC_PB3CR);
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#endif
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#if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 4))
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mtebc(PB4AP, CONFIG_SYS_EBC_PB4AP);
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mtebc(PB4CR, CONFIG_SYS_EBC_PB4CR);
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#endif
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#if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 5))
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mtebc(PB5AP, CONFIG_SYS_EBC_PB5AP);
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mtebc(PB5CR, CONFIG_SYS_EBC_PB5CR);
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#endif
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#if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 6))
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mtebc(PB6AP, CONFIG_SYS_EBC_PB6AP);
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mtebc(PB6CR, CONFIG_SYS_EBC_PB6CR);
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#endif
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#if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR) && !(CONFIG_SYS_INIT_DCACHE_CS == 7))
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mtebc(PB7AP, CONFIG_SYS_EBC_PB7AP);
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mtebc(PB7CR, CONFIG_SYS_EBC_PB7CR);
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#endif
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#if defined (CONFIG_SYS_EBC_CFG)
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mtebc(EBC0_CFG, CONFIG_SYS_EBC_CFG);
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#endif
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#if defined(CONFIG_WATCHDOG)
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val = mfspr(SPRN_TCR);
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
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val |= 0xb8000000; /* generate system reset after 1.34 seconds */
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#elif defined(CONFIG_440EPX)
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val |= 0xb0000000; /* generate system reset after 1.34 seconds */
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#else
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val |= 0xf0000000; /* generate system reset after 2.684 seconds */
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#endif
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#if defined(CONFIG_SYS_4xx_RESET_TYPE)
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val &= ~0x30000000; /* clear WRC bits */
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val |= CONFIG_SYS_4xx_RESET_TYPE << 28; /* set board specific WRC type */
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#endif
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mtspr(SPRN_TCR, val);
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val = mfspr(SPRN_TSR);
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val |= 0x80000000; /* enable watchdog timer */
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mtspr(SPRN_TSR, val);
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reset_4xx_watchdog();
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_440GX)
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/* Take the GX out of compatibility mode
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* Travis Sawyer, 9 Mar 2004
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* NOTE: 440gx user manual inconsistency here
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* Compatibility mode and Ethernet Clock select are not
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* correct in the manual
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*/
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mfsdr(SDR0_MFR, val);
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val &= ~0x10000000;
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mtsdr(SDR0_MFR,val);
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#endif /* CONFIG_440GX */
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#if defined(CONFIG_460EX)
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/*
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* Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and
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* clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata
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* regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA
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*/
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mfsdr(SDR0_AHB_CFG, val);
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val |= 0x80;
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val &= ~0x40;
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mtsdr(SDR0_AHB_CFG, val);
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mfsdr(SDR0_USB2HOST_CFG, val);
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val &= ~0xf00;
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val |= 0x400;
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mtsdr(SDR0_USB2HOST_CFG, val);
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#endif /* CONFIG_460EX */
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#if defined(CONFIG_405EX) || \
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defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
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defined(CONFIG_460SX)
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/*
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* Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
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*/
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mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
|
|
PLB4Ax_ACR_RDP_4DEEP);
|
|
mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) |
|
|
PLB4Ax_ACR_RDP_4DEEP);
|
|
#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
|
|
|
|
#ifndef CONFIG_SYS_GENERIC_BOARD
|
|
gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
|
|
|
|
/* Clear initial global data */
|
|
memset((void *)gd, 0, sizeof(gd_t));
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* initialize higher level parts of CPU like time base and timers
|
|
*/
|
|
int cpu_init_r (void)
|
|
{
|
|
#if defined(CONFIG_405GP)
|
|
uint pvr = get_pvr();
|
|
|
|
/*
|
|
* Set edge conditioning circuitry on PPC405GPr
|
|
* for compatibility to existing PPC405GP designs.
|
|
*/
|
|
if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
|
|
mtdcr(CPC0_ECR, 0x60606000);
|
|
}
|
|
#endif /* defined(CONFIG_405GP) */
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if defined(CONFIG_PCI) && \
|
|
(defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
|
|
defined(CONFIG_440GR) || defined(CONFIG_440GRX))
|
|
/*
|
|
* 440EP(x)/GR(x) PCI async/sync clocking restriction:
|
|
*
|
|
* In asynchronous PCI mode, the synchronous PCI clock must meet
|
|
* certain requirements. The following equation describes the
|
|
* relationship that must be maintained between the asynchronous PCI
|
|
* clock and synchronous PCI clock. Select an appropriate PCI:PLB
|
|
* ratio to maintain the relationship:
|
|
*
|
|
* AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz
|
|
*/
|
|
static int ppc4xx_pci_sync_clock_ok(u32 sync, u32 async)
|
|
{
|
|
if (((async - 1000000) > sync) || (sync > ((2 * async) - 1000000)))
|
|
return 0;
|
|
else
|
|
return 1;
|
|
}
|
|
|
|
int ppc4xx_pci_sync_clock_config(u32 async)
|
|
{
|
|
sys_info_t sys_info;
|
|
u32 sync;
|
|
int div;
|
|
u32 reg;
|
|
u32 spcid_val[] = {
|
|
CPR0_SPCID_SPCIDV0_DIV1, CPR0_SPCID_SPCIDV0_DIV2,
|
|
CPR0_SPCID_SPCIDV0_DIV3, CPR0_SPCID_SPCIDV0_DIV4 };
|
|
|
|
get_sys_info(&sys_info);
|
|
sync = sys_info.freqPCI;
|
|
|
|
/*
|
|
* First check if the equation above is met
|
|
*/
|
|
if (!ppc4xx_pci_sync_clock_ok(sync, async)) {
|
|
/*
|
|
* Reconfigure PCI sync clock to meet the equation.
|
|
* Start with highest possible PCI sync frequency
|
|
* (divider 1).
|
|
*/
|
|
for (div = 1; div <= 4; div++) {
|
|
sync = sys_info.freqPLB / div;
|
|
if (ppc4xx_pci_sync_clock_ok(sync, async))
|
|
break;
|
|
}
|
|
|
|
if (div <= 4) {
|
|
mtcpr(CPR0_SPCID, spcid_val[div]);
|
|
|
|
mfcpr(CPR0_ICFG, reg);
|
|
reg |= CPR0_ICFG_RLI_MASK;
|
|
mtcpr(CPR0_ICFG, reg);
|
|
|
|
/* do chip reset */
|
|
mtspr(SPRN_DBCR0, 0x20000000);
|
|
} else {
|
|
/* Impossible to configure the PCI sync clock */
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif
|