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345b77baca
As ppc4xx currently only supports the deprecated nand_spl infrastructure and nobody seems to have time / resources to port this over to the newer SPL infrastructure, lets remove NAND booting completely. This should not affect the "normal", non NAND-booting ppc4xx platforms that are currently supported. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Tirumala Marri <tmarri@apm.com> Cc: Matthias Fuchs <matthias.fuchs@esd.eu> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Tom Rini <trini@ti.com> Tested-by: Matthias Fuchs <matthias.fuchs@esd.eu>
82 lines
2.0 KiB
C
82 lines
2.0 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* define DEBUG for debugging output (obviously ;-)) */
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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extern void board_pll_init_f(void);
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static void cram_bcr_write(u32 wr_val)
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{
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wr_val <<= 2;
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/* set CRAM_CRE to 1 */
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gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
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/* Write BCR to CRAM on CS1 */
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out32(wr_val + 0x00200000, 0);
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debug("CRAM VAL: %08x for CS1 ", wr_val + 0x00200000);
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/* Write BCR to CRAM on CS2 */
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out32(wr_val + 0x02200000, 0);
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debug("CRAM VAL: %08x for CS2\n", wr_val + 0x02200000);
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sync();
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eieio();
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/* set CRAM_CRE back to 0 (normal operation) */
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gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
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return;
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}
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phys_size_t initdram(int board_type)
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{
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int i;
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u32 val;
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/* 1. EBC need to program READY, CLK, ADV for ASync mode */
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gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
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gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
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gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
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gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
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/* 2. EBC in Async mode */
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mtebc(PB1AP, 0x078F1EC0);
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mtebc(PB2AP, 0x078F1EC0);
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mtebc(PB1CR, 0x000BC000);
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mtebc(PB2CR, 0x020BC000);
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/* 3. Set CRAM in Sync mode */
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cram_bcr_write(0x7012); /* CRAM burst setting */
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/* 4. EBC in Sync mode */
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mtebc(PB1AP, 0x9C0201C0);
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mtebc(PB2AP, 0x9C0201C0);
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/* Set GPIO pins back to alternate function */
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gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
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gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
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/* Config EBC to use RDY */
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mfsdr(SDR0_ULTRA0, val);
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mtsdr(SDR0_ULTRA0, val | SDR_ULTRA0_EBCRDYEN);
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/* Wait a short while, since for NAND booting this is too fast */
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for (i=0; i<200000; i++)
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;
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return (CONFIG_SYS_MBYTES_RAM << 20);
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}
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