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7981449280
Split the SATA clock enabling function and add PCI express clock enabling function. The SATA clock enabling function starts up the 100MHz SATA reference PLL in ENET_PLL register, but the code can be re-used to enable the 125MHz PCIe reference in ENET_PLL, so pull this code into separate function. Moreover, add the PCIe clock enabling code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
63 lines
1.2 KiB
C
63 lines
1.2 KiB
C
/*
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* (C) Copyright 2009
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_H
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#define __ASM_ARCH_CLOCK_H
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#include <common.h>
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#ifdef CONFIG_SYS_MX6_HCLK
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#define MXC_HCLK CONFIG_SYS_MX6_HCLK
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#else
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#define MXC_HCLK 24000000
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#endif
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#ifdef CONFIG_SYS_MX6_CLK32
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#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
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#else
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#define MXC_CLK32 32768
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#endif
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enum mxc_clock {
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MXC_ARM_CLK = 0,
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MXC_PER_CLK,
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MXC_AHB_CLK,
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MXC_IPG_CLK,
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MXC_IPG_PERCLK,
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MXC_UART_CLK,
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MXC_CSPI_CLK,
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MXC_AXI_CLK,
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MXC_EMI_SLOW_CLK,
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MXC_DDR_CLK,
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MXC_ESDHC_CLK,
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MXC_ESDHC2_CLK,
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MXC_ESDHC3_CLK,
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MXC_ESDHC4_CLK,
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MXC_SATA_CLK,
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MXC_NFC_CLK,
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MXC_I2C_CLK,
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};
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enum enet_freq {
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ENET_25MHz,
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ENET_50MHz,
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ENET_100MHz,
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ENET_125MHz,
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};
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u32 imx_get_uartclk(void);
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u32 imx_get_fecclk(void);
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unsigned int mxc_get_clock(enum mxc_clock clk);
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void enable_ocotp_clk(unsigned char enable);
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void enable_usboh3_clk(unsigned char enable);
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int enable_sata_clock(void);
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int enable_pcie_clock(void);
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
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void enable_ipu_clock(void);
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int enable_fec_anatop_clock(enum enet_freq freq);
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#endif /* __ASM_ARCH_CLOCK_H */
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