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665cb18ea6
The MTRRs are normally set up in U-Boot proper, so avoid setting them up in SPL as well. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
35 lines
726 B
C
35 lines
726 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/mtrr.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Get the top of usable RAM */
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__weak ulong board_get_usable_ram_top(ulong total_size)
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{
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return gd->ram_size;
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}
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int init_cache_f_r(void)
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{
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#if (CONFIG_IS_ENABLED(X86_32BIT_INIT) || \
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(!defined(CONFIG_SPL_BUILD) && \
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!CONFIG_IS_ENABLED(CONFIG_X86_RUN_64BIT))) && \
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!defined(CONFIG_HAVE_FSP)
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int ret;
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ret = mtrr_commit(false);
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/* If MTRR MSR is not implemented by the processor, just ignore it */
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if (ret && ret != -ENOSYS)
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return ret;
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#endif
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/* Initialise the CPU cache(s) */
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return init_cache();
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}
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