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7fb3e7a2d6
Includes board config file, documentation, maintainer and boards.cfg entries, and board specific files in vendor dir. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
135 lines
3.4 KiB
C
135 lines
3.4 KiB
C
/*
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* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
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*
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* Copyright (C) 2011 Matrix Vision GmbH
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* Andre Schwarz <andre.schwarz@matrix-vision.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <mpc83xx.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/fsl_mpc83xx_serdes.h>
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#include "mergerbox.h"
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#include "fpga.h"
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#include "../common/mv_common.h"
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static struct pci_region pci_regions[] = {
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{
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.bus_start = CONFIG_SYS_PCI_MEM_BASE,
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.phys_start = CONFIG_SYS_PCI_MEM_PHYS,
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.size = CONFIG_SYS_PCI_MEM_SIZE,
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.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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.bus_start = CONFIG_SYS_PCI_MMIO_BASE,
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.phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
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.size = CONFIG_SYS_PCI_MMIO_SIZE,
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.flags = PCI_REGION_MEM
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},
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{
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.bus_start = CONFIG_SYS_PCI_IO_BASE,
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.phys_start = CONFIG_SYS_PCI_IO_PHYS,
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.size = CONFIG_SYS_PCI_IO_SIZE,
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.flags = PCI_REGION_IO
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}
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};
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static struct pci_region pcie_regions_0[] = {
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{
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.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
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.size = CONFIG_SYS_PCIE1_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
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.size = CONFIG_SYS_PCIE1_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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static struct pci_region pcie_regions_1[] = {
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{
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.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
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.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
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.size = CONFIG_SYS_PCIE2_MEM_SIZE,
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.flags = PCI_REGION_MEM,
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},
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{
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.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
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.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
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.size = CONFIG_SYS_PCIE2_IO_SIZE,
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.flags = PCI_REGION_IO,
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},
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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volatile sysconf83xx_t *sysconf = &immr->sysconf;
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volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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volatile law83xx_t *pcie_law = sysconf->pcielaw;
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struct pci_region *reg[] = { pci_regions };
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struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
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volatile gpio83xx_t *gpio;
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gpio = (gpio83xx_t *)&immr->gpio[0];
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gpio->dat = MV_GPIO1_DAT;
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gpio->odr = MV_GPIO1_ODE;
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gpio->dir = MV_GPIO1_OUT;
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gpio = (gpio83xx_t *)&immr->gpio[1];
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gpio->dat = MV_GPIO2_DAT;
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gpio->odr = MV_GPIO2_ODE;
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gpio->dir = MV_GPIO2_OUT;
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printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
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immr->sysconf.sicrl);
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/* Enable PCI_CLK[0:1] */
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clk->occr |= 0xc0000000;
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udelay(2000);
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mergerbox_init_fpga();
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mv_load_fpga();
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mergerbox_tft_dim(0);
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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udelay(2000);
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mpc83xx_pci_init(1, reg);
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/* Deassert the resets in the control register */
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out_be32(&sysconf->pecr1, 0xE0008000);
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out_be32(&sysconf->pecr2, 0xE0008000);
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udelay(2000);
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out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
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out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
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out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
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mpc83xx_pcie_init(2, pcie_reg);
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}
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