mirror of
https://github.com/smaeul/u-boot.git
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fc14fbace4
As the CPU name is not configurable, using CPU string directly Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
167 lines
5.7 KiB
C
167 lines
5.7 KiB
C
/*
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* Chip-specific header file for the AT91SAM9x5 family
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*
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* Copyright (C) 2012 Atmel Corporation.
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*
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* Definitions for the SoC:
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* AT91SAM9x5
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __AT91SAM9X5_H__
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#define __AT91SAM9X5_H__
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define ATMEL_ID_SYS 1 /* System Controller Interrupt */
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#define ATMEL_ID_PIOAB 2 /* Parallel I/O Controller A and B */
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#define ATMEL_ID_PIOCD 3 /* Parallel I/O Controller C and D */
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#define ATMEL_ID_SMD 4 /* SMD Soft Modem (SMD) */
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#define ATMEL_ID_USART0 5 /* USART 0 */
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#define ATMEL_ID_USART1 6 /* USART 1 */
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#define ATMEL_ID_USART2 7 /* USART 2 */
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#define ATMEL_ID_TWI0 9 /* Two-Wire Interface 0 */
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#define ATMEL_ID_TWI1 10 /* Two-Wire Interface 1 */
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#define ATMEL_ID_TWI2 11 /* Two-Wire Interface 2 */
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#define ATMEL_ID_HSMCI0 12 /* High Speed Multimedia Card Interface 0 */
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#define ATMEL_ID_SPI0 13 /* Serial Peripheral Interface 0 */
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#define ATMEL_ID_SPI1 14 /* Serial Peripheral Interface 1 */
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#define ATMEL_ID_UART0 15 /* UART 0 */
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#define ATMEL_ID_UART1 16 /* UART 1 */
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#define ATMEL_ID_TC01 17 /* Timer Counter 0, 1, 2, 3, 4 and 5 */
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#define ATMEL_ID_PWM 18 /* Pulse Width Modulation Controller */
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#define ATMEL_ID_ADC 19 /* ADC Controller */
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#define ATMEL_ID_DMAC0 20 /* DMA Controller 0 */
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#define ATMEL_ID_DMAC1 21 /* DMA Controller 1 */
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#define ATMEL_ID_UHPHS 22 /* USB Host High Speed */
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#define ATMEL_ID_UDPHS 23 /* USB Device High Speed */
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#define ATMEL_ID_EMAC0 24 /* Ethernet MAC0 */
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#define ATMEL_ID_LCDC 25 /* LCD Controller */
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#define ATMEL_ID_HSMCI1 26 /* High Speed Multimedia Card Interface 1 */
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#define ATMEL_ID_EMAC1 27 /* Ethernet MAC1 */
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#define ATMEL_ID_SSC 28 /* Synchronous Serial Controller */
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#define ATMEL_ID_IRQ 31 /* Advanced Interrupt Controller */
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/*
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* User Peripheral physical base addresses.
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*/
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#define ATMEL_BASE_SPI0 0xf0000000
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#define ATMEL_BASE_SPI1 0xf0004000
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#define ATMEL_BASE_HSMCI0 0xf0008000
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#define ATMEL_BASE_HSMCI1 0xf000c000
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#define ATMEL_BASE_SSC 0xf0010000
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#define ATMEL_BASE_CAN0 0xf8000000
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#define ATMEL_BASE_CAN1 0xf8004000
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#define ATMEL_BASE_TC0 0xf8008000
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#define ATMEL_BASE_TC1 0xf8008040
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#define ATMEL_BASE_TC2 0xf8008080
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#define ATMEL_BASE_TC3 0xf800c000
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#define ATMEL_BASE_TC4 0xf800c040
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#define ATMEL_BASE_TC5 0xf800c080
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#define ATMEL_BASE_TWI0 0xf8010000
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#define ATMEL_BASE_TWI1 0xf8014000
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#define ATMEL_BASE_TWI2 0xf8018000
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#define ATMEL_BASE_USART0 0xf801c000
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#define ATMEL_BASE_USART1 0xf8020000
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#define ATMEL_BASE_USART2 0xf8024000
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#define ATMEL_BASE_USART3 0xf8028000
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#define ATMEL_BASE_EMAC0 0xf802c000
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#define ATMEL_BASE_EMAC1 0xf8030000
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#define ATMEL_BASE_PWM 0xf8034000
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#define ATMEL_BASE_LCDC 0xf8038000
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#define ATMEL_BASE_UDPHS 0xf803c000
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#define ATMEL_BASE_UART0 0xf8040000
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#define ATMEL_BASE_UART1 0xf8044000
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#define ATMEL_BASE_ISI 0xf8048000
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#define ATMEL_BASE_ADC 0xf804c000
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#define ATMEL_BASE_SYS 0xffffc000
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/*
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* System Peripherals
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*/
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#define ATMEL_BASE_MATRIX 0xffffde00
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#define ATMEL_BASE_PMECC 0xffffe000
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#define ATMEL_BASE_PMERRLOC 0xffffe600
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#define ATMEL_BASE_DDRSDRC 0xffffe800
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#define ATMEL_BASE_SMC 0xffffea00
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#define ATMEL_BASE_DMAC0 0xffffec00
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#define ATMEL_BASE_DMAC1 0xffffee00
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#define ATMEL_BASE_AIC 0xfffff000
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#define ATMEL_BASE_DBGU 0xfffff200
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#define ATMEL_BASE_PIOA 0xfffff400
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#define ATMEL_BASE_PIOB 0xfffff600
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#define ATMEL_BASE_PIOC 0xfffff800
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#define ATMEL_BASE_PIOD 0xfffffa00
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#define ATMEL_BASE_PMC 0xfffffc00
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#define ATMEL_BASE_RSTC 0xfffffe00
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#define ATMEL_BASE_SHDWC 0xfffffe10
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#define ATMEL_BASE_PIT 0xfffffe30
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#define ATMEL_BASE_WDT 0xfffffe40
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#define ATMEL_BASE_GPBR 0xfffffe60
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#define ATMEL_BASE_RTC 0xfffffeb0
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/*
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* Internal Memory.
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*/
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#define ATMEL_BASE_ROM 0x00100000 /* Internal ROM base address */
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#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */
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#define ATMEL_BASE_SMD 0x00400000 /* SMD Controller */
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#define ATMEL_BASE_UDPHS_FIFO 0x00500000 /* USB Device HS controller */
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#define ATMEL_BASE_OHCI 0x00600000 /* USB Host controller (OHCI) */
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#define ATMEL_BASE_EHCI 0x00700000 /* USB Host controller (EHCI) */
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/* 9x5 series chip id definitions */
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#define ARCH_ID_AT91SAM9X5 0x819a05a0
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#define ARCH_ID_VERSION_MASK 0x1f
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#define ARCH_EXID_AT91SAM9G15 0x00000000
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#define ARCH_EXID_AT91SAM9G35 0x00000001
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#define ARCH_EXID_AT91SAM9X35 0x00000002
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#define ARCH_EXID_AT91SAM9G25 0x00000003
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#define ARCH_EXID_AT91SAM9X25 0x00000004
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#define cpu_is_at91sam9x5() (get_chip_id() == ARCH_ID_AT91SAM9X5)
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#define cpu_is_at91sam9g15() (cpu_is_at91sam9x5() && \
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(get_extension_chip_id() == ARCH_EXID_AT91SAM9G15))
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#define cpu_is_at91sam9g25() (cpu_is_at91sam9x5() && \
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(get_extension_chip_id() == ARCH_EXID_AT91SAM9G25))
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#define cpu_is_at91sam9g35() (cpu_is_at91sam9x5() && \
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(get_extension_chip_id() == ARCH_EXID_AT91SAM9G35))
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#define cpu_is_at91sam9x25() (cpu_is_at91sam9x5() && \
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(get_extension_chip_id() == ARCH_EXID_AT91SAM9X25))
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#define cpu_is_at91sam9x35() (cpu_is_at91sam9x5() && \
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(get_extension_chip_id() == ARCH_EXID_AT91SAM9X35))
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/*
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* Cpu Name
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*/
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#define ATMEL_CPU_NAME get_cpu_name()
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/*
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* Other misc defines
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*/
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#define ATMEL_PIO_PORTS 4
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#define CPU_HAS_PIO3
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#define PIO_SCDR_DIV (0x3fff << 0) /* Slow Clock Divider Mask */
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#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
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#define ATMEL_ID_UHP ATMEL_ID_UHPHS
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/*
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* at91sam9x5 specific prototypes
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*/
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#ifndef __ASSEMBLY__
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unsigned int get_chip_id(void);
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unsigned int get_extension_chip_id(void);
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unsigned int has_emac1(void);
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unsigned int has_emac0(void);
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unsigned int has_lcdc(void);
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char *get_cpu_name(void);
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#endif
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#endif
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