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02cd449f0b
This patch rewrites the mtmips architecture with the following changes: 1. Move MT7628 soc parts into a subfolder. 2. Lock parts of D-Cache as temporary stack. 3. Reimplement DDR initialization in C language. 4. Reimplement DDR calibration in a clear logic. 5. Add full support for auto size detection for DDR1 and DDR2. 6. Use accurate CPU clock depending on the input xtal frequency for timer and delay functions. Note: print_cpuinfo() has incompatible parts with MT7620 so it's moved into mt7628 subfolder. Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
162 lines
3.4 KiB
ArmAsm
162 lines
3.4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*/
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#include <config.h>
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#include <asm-offsets.h>
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#include <asm/cacheops.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include "mt7628.h"
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/* Set temporary stack address range */
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#ifndef CONFIG_SYS_INIT_SP_ADDR
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
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CONFIG_SYS_INIT_SP_OFFSET)
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#endif
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#define CACHE_STACK_SIZE 0x4000
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#define CACHE_STACK_BASE (CONFIG_SYS_INIT_SP_ADDR - CACHE_STACK_SIZE)
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#define DELAY_USEC(us) ((58 * (us)) / 3)
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.set noreorder
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LEAF(mips_sram_init)
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/* Setup CPU PLL */
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li t0, DELAY_USEC(1000000)
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li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG)
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li t2, KSEG1ADDR(SYSCTL_BASE + SYSCTL_CLKCFG0_REG)
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_check_rom_status:
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lw t3, 0(t1)
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andi t3, t3, 1
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bnez t3, _rom_normal
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subu t0, t0, 1
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bnez t0, _check_rom_status
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nop
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lw t3, 0(t2)
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ori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)
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xori t3, CPU_PLL_FROM_BBP
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b _cpu_pll_done
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nop
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_rom_normal:
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lw t3, 0(t2)
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ori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL | \
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DIS_BBP_SLEEP | EN_BBP_CLK)
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xori t3, (CPU_PLL_FROM_BBP | CPU_PLL_FROM_XTAL)
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_cpu_pll_done:
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sw t3, 0(t2)
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li t2, KSEG1ADDR(RBUSCTL_BASE + RBUSCTL_DYN_CFG0_REG)
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lw t3, 0(t2)
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ori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M)
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xori t3, t3, (CPU_FDIV_M | CPU_FFRAC_M)
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ori t3, t3, ((1 << CPU_FDIV_S) | (1 << CPU_FFRAC_S))
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sw t3, 0(t2)
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/* Clear WST & SPR bits in ErrCtl */
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mfc0 t0, CP0_ECC
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ins t0, zero, 30, 2
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mtc0 t0, CP0_ECC
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ehb
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/* Simply initialize I-Cache */
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li a0, 0
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li a1, CONFIG_SYS_ICACHE_SIZE
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mtc0 zero, CP0_TAGLO /* Zero to DDataLo */
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1: cache INDEX_STORE_TAG_I, 0(a0)
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addiu a0, CONFIG_SYS_ICACHE_LINE_SIZE
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bne a0, a1, 1b
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nop
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/* Simply initialize D-Cache */
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li a0, 0
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li a1, CONFIG_SYS_DCACHE_SIZE
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mtc0 zero, CP0_TAGLO, 2
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2: cache INDEX_STORE_TAG_D, 0(a0)
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addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE
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bne a0, a1, 2b
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nop
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/* Set KSEG0 Cachable */
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mfc0 t0, CP0_CONFIG
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and t0, t0, MIPS_CONF_IMPL
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or t0, t0, CONF_CM_CACHABLE_NONCOHERENT
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mtc0 t0, CP0_CONFIG
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ehb
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/* Lock D-Cache */
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PTR_LI a0, CACHE_STACK_BASE /* D-Cache lock base */
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li a1, CACHE_STACK_SIZE /* D-Cache lock size */
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li a2, 0x1ffff800 /* Mask of DTagLo[PTagLo] */
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3:
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/* Lock one cacheline */
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and t0, a0, a2
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ori t0, 0xe0 /* Valid & Dirty & Lock bits */
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mtc0 t0, CP0_TAGLO, 2 /* Write to DTagLo */
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ehb
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cache INDEX_STORE_TAG_D, 0(a0)
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addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE
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sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
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bnez a1, 3b
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nop
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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jr ra
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nop
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END(mips_sram_init)
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NESTED(lowlevel_init, 0, ra)
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/* Save ra and do real lowlevel initialization */
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move s0, ra
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PTR_LA t9, mt7628_init
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jalr t9
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nop
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move ra, s0
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#if CONFIG_IS_ENABLED(INIT_STACK_WITHOUT_MALLOC_F)
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/* Set malloc base */
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li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15)
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PTR_S t0, GD_MALLOC_BASE(k0) # gd->malloc_base offset
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#endif
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/* Write back data in locked cache to DRAM */
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PTR_LI a0, CACHE_STACK_BASE /* D-Cache unlock base */
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li a1, CACHE_STACK_SIZE /* D-Cache unlock size */
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1:
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cache HIT_WRITEBACK_INV_D, 0(a0)
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addiu a0, CONFIG_SYS_DCACHE_LINE_SIZE
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sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
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bnez a1, 1b
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nop
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/* Set KSEG0 Uncached */
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mfc0 t0, CP0_CONFIG
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and t0, t0, MIPS_CONF_IMPL
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or t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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ehb
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jr ra
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nop
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END(lowlevel_init)
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