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			224 lines
		
	
	
		
			5.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			224 lines
		
	
	
		
			5.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * (C) Copyright 2010
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|  * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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|  *
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|  * (C) Copyright 2009 Freescale Semiconductor, Inc.
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|  *
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|  * See file CREDITS for list of people who contributed to this
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|  * project.
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|  *
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|  * This program is free software; you can redistribute it and/or
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|  * modify it under the terms of the GNU General Public License as
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|  * published by the Free Software Foundation; either version 2 of
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|  * the License, or (at your option) any later version.
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|  *
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|  * This program is distributed in the hope that it will be useful,
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|  * but WITHOUT ANY WARRANTY; without even the implied warranty of
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|  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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|  * GNU General Public License for more details.
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|  *
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|  * You should have received a copy of the GNU General Public License
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|  * along with this program; if not, write to the Free Software
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|  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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|  * MA 02111-1307 USA
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|  */
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| 
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| 
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| #ifndef __MC13892_H__
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| #define __MC13892_H__
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| 
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| /* REG_CHARGE */
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| 
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| #define VCHRG0		(1 << 0)
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| #define VCHRG1		(1 << 1)
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| #define VCHRG2		(1 << 2)
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| #define ICHRG0		(1 << 3)
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| #define ICHRG1		(1 << 4)
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| #define ICHRG2		(1 << 5)
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| #define ICHRG3		(1 << 6)
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| #define TREN		(1 << 7)
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| #define ACKLPB		(1 << 8)
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| #define THCHKB		(1 << 9)
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| #define FETOVRD		(1 << 10)
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| #define FETCTRL		(1 << 11)
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| #define RVRSMODE	(1 << 13)
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| #define PLIM0		(1 << 15)
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| #define PLIM1		(1 << 16)
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| #define PLIMDIS		(1 << 17)
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| #define CHRGLEDEN	(1 << 18)
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| #define CHGTMRRST	(1 << 19)
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| #define CHGRESTART	(1 << 20)
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| #define CHGAUTOB	(1 << 21)
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| #define CYCLB		(1 << 22)
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| #define CHGAUTOVIB	(1 << 23)
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| 
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| /* REG_SETTING_0/1 */
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| #define VO_1_20V	0
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| #define VO_1_30V	1
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| #define VO_1_50V	2
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| #define VO_1_80V	3
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| #define VO_1_10V	4
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| #define VO_2_00V	5
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| #define VO_2_77V	6
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| #define VO_2_40V	7
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| 
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| #define VIOL		2
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| #define VDIG		4
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| #define VGEN		6
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| 
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| /* SWxMode for Normal/Standby Mode */
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| #define SWMODE_OFF_OFF		0
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| #define SWMODE_PWM_OFF		1
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| #define SWMODE_PWMPS_OFF	2
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| #define SWMODE_PFM_OFF		3
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| #define SWMODE_AUTO_OFF		4
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| #define SWMODE_PWM_PWM		5
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| #define SWMODE_PWM_AUTO		6
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| #define SWMODE_AUTO_AUTO	8
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| #define SWMODE_PWM_PWMPS	9
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| #define SWMODE_PWMS_PWMPS	10
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| #define SWMODE_PWMS_AUTO	11
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| #define SWMODE_AUTO_PFM		12
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| #define SWMODE_PWM_PFM		13
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| #define SWMODE_PWMS_PFM		14
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| #define SWMODE_PFM_PFM		15
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| #define SWMODE_MASK		0x0F
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| 
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| #define SWMODE1_SHIFT		0
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| #define SWMODE2_SHIFT		10
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| #define SWMODE3_SHIFT		0
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| #define SWMODE4_SHIFT		8
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| 
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| /* Fields in REG_SETTING_1 */
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| #define VVIDEO_2_7	(0 << 2)
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| #define VVIDEO_2_775	(1 << 2)
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| #define VVIDEO_2_5	(2 << 2)
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| #define VVIDEO_2_6	(3 << 2)
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| #define VVIDEO_MASK	(3 << 2)
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| #define VAUDIO_2_3	(0 << 4)
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| #define VAUDIO_2_5	(1 << 4)
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| #define VAUDIO_2_775	(2 << 4)
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| #define VAUDIO_3_0	(3 << 4)
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| #define VAUDIO_MASK	(3 << 4)
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| #define VSD_1_8		(0 << 6)
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| #define VSD_2_0		(1 << 6)
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| #define VSD_2_6		(2 << 6)
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| #define VSD_2_7		(3 << 6)
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| #define VSD_2_8		(4 << 6)
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| #define VSD_2_9		(5 << 6)
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| #define VSD_3_0		(6 << 6)
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| #define VSD_3_15	(7 << 6)
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| #define VSD_MASK	(7 << 6)
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| #define VGEN1_1_2	0
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| #define VGEN1_1_5	1
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| #define VGEN1_2_775	2
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| #define VGEN1_3_15	3
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| #define VGEN1_MASK	3
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| #define VGEN2_1_2	(0 << 6)
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| #define VGEN2_1_5	(1 << 6)
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| #define VGEN2_1_6	(2 << 6)
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| #define VGEN2_1_8	(3 << 6)
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| #define VGEN2_2_7	(4 << 6)
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| #define VGEN2_2_8	(5 << 6)
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| #define VGEN2_3_0	(6 << 6)
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| #define VGEN2_3_15	(7 << 6)
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| #define VGEN2_MASK	(7 << 6)
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| 
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| /* Fields in REG_SETTING_1 */
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| #define VGEN3_1_8	(0 << 14)
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| #define VGEN3_2_9	(1 << 14)
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| #define VGEN3_MASK	(1 << 14)
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| #define VDIG_1_05	(0 << 4)
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| #define VDIG_1_25	(1 << 4)
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| #define VDIG_1_65	(2 << 4)
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| #define VDIG_1_8	(3 << 4)
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| #define VDIG_MASK	(3 << 4)
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| #define VCAM_2_5	(0 << 16)
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| #define VCAM_2_6	(1 << 16)
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| #define VCAM_2_75	(2 << 16)
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| #define VCAM_3_0	(3 << 16)
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| #define VCAM_MASK	(3 << 16)
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| 
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| /* Reg Mode 0 */
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| #define VGEN1EN		(1 << 0)
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| #define VGEN1STBY	(1 << 1)
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| #define VGEN1MODE	(1 << 2)
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| #define VIOHIEN		(1 << 3)
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| #define VIOHISTBY	(1 << 4)
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| #define VDIGEN		(1 << 9)
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| #define VDIGSTBY	(1 << 10)
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| #define VGEN2EN		(1 << 12)
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| #define VGEN2STBY	(1 << 13)
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| #define VGEN2MODE	(1 << 14)
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| #define VPLLEN		(1 << 15)
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| #define VPLLSTBY	(1 << 16)
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| #define VUSBEN		(1 << 18)
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| #define VUSBSTBY	(1 << 19)
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| 
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| /* Reg Mode 1 */
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| #define VGEN3EN		(1 << 0)
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| #define VGEN3STBY	(1 << 1)
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| #define VGEN3MODE	(1 << 2)
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| #define VGEN3CONFIG	(1 << 3)
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| #define VCAMEN		(1 << 6)
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| #define VCAMSTBY	(1 << 7)
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| #define VCAMMODE	(1 << 8)
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| #define VCAMCONFIG	(1 << 9)
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| #define VVIDEOEN	(1 << 12)
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| #define VIDEOSTBY	(1 << 13)
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| #define VVIDEOMODE	(1 << 14)
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| #define VAUDIOEN	(1 << 15)
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| #define VAUDIOSTBY	(1 << 16)
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| #define VSDEN		(1 << 18)
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| #define VSDSTBY		(1 << 19)
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| #define VSDMODE		(1 << 20)
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| 
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| /* Reg Power Control 2*/
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| #define WDIRESET	(1 << 12)
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| 
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| /* SWx Output Volts */
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| #define SWX_OUT_MASK	0x1F
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| #define SWX_OUT_1_25	0x1A
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| #define SWX_OUT_1_30    0X1C
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| 
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| /* Buck Switchers (SW1,2,3,4) Output Voltage */
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| /*
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|  * NOTE: These values are for SWxHI = 0,
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|  * SWxHI = 1 adds 0.5V to the desired voltage
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|  */
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| #define SWx_0_600V	0
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| #define SWx_0_625V	1
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| #define SWx_0_650V	2
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| #define SWx_0_675V	3
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| #define SWx_0_700V	4
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| #define SWx_0_725V	5
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| #define SWx_0_750V	6
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| #define SWx_0_775V	7
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| #define SWx_0_800V	8
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| #define SWx_0_825V	9
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| #define SWx_0_850V	10
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| #define SWx_0_875V	11
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| #define SWx_0_900V	12
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| #define SWx_0_925V	13
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| #define SWx_0_950V	14
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| #define SWx_0_975V	15
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| #define SWx_1_000V	16
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| #define SWx_1_025V	17
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| #define SWx_1_050V	18
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| #define SWx_1_075V	19
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| #define SWx_1_100V	20
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| #define SWx_1_125V	21
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| #define SWx_1_150V	22
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| #define SWx_1_175V	23
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| #define SWx_1_200V	24
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| #define SWx_1_225V	25
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| #define SWx_1_250V	26
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| #define SWx_1_275V	27
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| #define SWx_1_300V	28
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| #define SWx_1_325V	29
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| #define SWx_1_350V	30
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| #define SWx_1_375V	31
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| #define SWx_VOLT_MASK	0x1F
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| 
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| #endif
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