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9452d58e10
This patch converts the dart6ul ethernet support to DM_ETH and cleans up the legacy ethernet code. The clean up, more specifically: * moves the fec2 node and pin definition to the carrier board DTS since the phy associated with it is on the carrier board and not on the SoM; * add the reset pin associated to each phy; * separate the ethernet, mdio and reset pins of each fec so that they are easier to reference; * add clock properties to the phy nodes since they are connected to the 50Mhz ENET[12]_TX_CLK clock of the SoC; * remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty. Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
88 lines
1.9 KiB
Plaintext
88 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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* Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
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*/
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/dts-v1/;
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#include "imx6ull.dtsi"
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#include "imx6ull-dart-6ul.dtsi"
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/ {
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model = "Variscite DART-6UL Evaluation Kit";
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compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
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};
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&mdio1 {
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/* KSZ8081RNB (carrier-board) */
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ethphy1: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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clocks = <&clks IMX6UL_CLK_ENET2_REF>;
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clock-names = "rmii-ref";
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micrel,led-mode = <1>;
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max-speed = <100>;
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reg = <3>;
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_rst>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <100>;
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status = "okay";
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};
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&usdhc2 {
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1_id>;
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dr_mode = "otg";
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_usb_otg1_id: usbotg1idgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
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>;
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};
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pinctrl_enet2_mdio: mdio_enet2_grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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>;
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};
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pinctrl_enet2_rst: enet2-rst-grp {
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fsl,pins = <
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MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0
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>;
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};
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};
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