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https://github.com/smaeul/u-boot.git
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51087a320d
Implement various CPU related functions. I'm actually just using it to get cpu clock frequency. Tested-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
118 lines
2.3 KiB
C
118 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2024 Jiaxun Yang <jiaxun.yang@flygoat.com>
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*/
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#include <clk.h>
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#include <cpu.h>
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#include <dm.h>
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#include <errno.h>
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#include <linux/bitops.h>
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#include <linux/err.h>
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#include <asm/arch/core.h>
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static int xtensa_cpu_get_desc(const struct udevice *dev, char *buf, int size)
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{
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const char *cpu = XCHAL_CORE_ID;
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if (!cpu || size < (strlen(cpu) + 1))
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return -ENOSPC;
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strcpy(buf, cpu);
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return 0;
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}
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static int xtensa_cpu_get_info(const struct udevice *dev, struct cpu_info *info)
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{
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struct cpu_plat *plat = dev_get_parent_plat(dev);
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info->cpu_freq = plat->timebase_freq;
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#if XCHAL_HAVE_PTP_MMU
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info->features |= BIT(CPU_FEAT_MMU);
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#endif
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#if XCHAL_ICACHE_SIZE || XCHAL_DCACHE_SIZE
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info->features |= BIT(CPU_FEAT_L1_CACHE);
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#endif
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return 0;
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}
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static int xtensa_cpu_get_count(const struct udevice *dev)
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{
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ofnode node;
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int num = 0;
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ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
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const char *device_type;
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/* skip if hart is marked as not available in the device tree */
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if (!ofnode_is_enabled(node))
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continue;
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device_type = ofnode_read_string(node, "device_type");
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if (!device_type)
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continue;
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if (strcmp(device_type, "cpu") == 0)
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num++;
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}
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return num;
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}
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static int xtensa_cpu_bind(struct udevice *dev)
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{
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struct cpu_plat *plat = dev_get_parent_plat(dev);
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plat->cpu_id = dev_read_addr(dev);
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return 0;
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}
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static int xtensa_cpu_probe(struct udevice *dev)
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{
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int ret = 0;
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struct clk clk;
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struct cpu_plat *plat = dev_get_parent_plat(dev);
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asm volatile ("rsr %0, 176\n"
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"rsr %1, 208\n"
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: "=r"(plat->id[0]), "=r"(plat->id[1]));
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/* Get a clock if it exists */
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ret = clk_get_by_index(dev, 0, &clk);
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if (!ret) {
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ret = clk_enable(&clk);
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if (ret && (ret != -ENOSYS || ret != -ENOTSUPP))
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return ret;
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ret = clk_get_rate(&clk);
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if (!IS_ERR_VALUE(ret))
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plat->timebase_freq = ret;
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}
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return 0;
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}
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static const struct cpu_ops xtensa_cpu_ops = {
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.get_desc = xtensa_cpu_get_desc,
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.get_info = xtensa_cpu_get_info,
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.get_count = xtensa_cpu_get_count,
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};
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static const struct udevice_id xtensa_cpu_ids[] = {
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{ .compatible = "cdns,xtensa-cpu" },
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{ }
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};
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U_BOOT_DRIVER(xtensa_cpu) = {
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.name = "xtensa_cpu",
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.id = UCLASS_CPU,
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.of_match = xtensa_cpu_ids,
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.bind = xtensa_cpu_bind,
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.probe = xtensa_cpu_probe,
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.ops = &xtensa_cpu_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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