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53677ef18e
This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
411 lines
10 KiB
C
411 lines
10 KiB
C
/**
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* @file IxEthAccMii.c
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*
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* @author Intel Corporation
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* @date
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*
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* @brief MII control functions
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*
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* Design Notes:
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*
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* IXP400 SW Release version 2.0
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*
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* -- Copyright Notice --
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*
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* @par
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* Copyright 2001-2005, Intel Corporation.
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* All rights reserved.
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*
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* @par
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the Intel Corporation nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @par
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* -- End of Copyright Notice --
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*/
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#include "IxOsal.h"
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#include "IxEthAcc.h"
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#include "IxEthAcc_p.h"
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#include "IxEthAccMac_p.h"
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#include "IxEthAccMii_p.h"
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PRIVATE UINT32 miiBaseAddressVirt;
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PRIVATE IxOsalMutex miiAccessLock;
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PUBLIC UINT32 ixEthAccMiiRetryCount = IX_ETH_ACC_MII_TIMEOUT_10TH_SECS;
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PUBLIC UINT32 ixEthAccMiiAccessTimeout = IX_ETH_ACC_MII_10TH_SEC_IN_MILLIS;
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/* -----------------------------------
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* private function prototypes
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*/
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PRIVATE void
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ixEthAccMdioCmdWrite(UINT32 mdioCommand);
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PRIVATE void
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ixEthAccMdioCmdRead(UINT32 *data);
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PRIVATE void
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ixEthAccMdioStatusRead(UINT32 *data);
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PRIVATE void
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ixEthAccMdioCmdWrite(UINT32 mdioCommand)
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{
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REG_WRITE(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_CMD_1,
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mdioCommand & 0xff);
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REG_WRITE(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_CMD_2,
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(mdioCommand >> 8) & 0xff);
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REG_WRITE(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_CMD_3,
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(mdioCommand >> 16) & 0xff);
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REG_WRITE(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_CMD_4,
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(mdioCommand >> 24) & 0xff);
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}
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PRIVATE void
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ixEthAccMdioCmdRead(UINT32 *data)
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{
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UINT32 regval;
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REG_READ(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_CMD_1,
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regval);
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*data = regval & 0xff;
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REG_READ(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_CMD_2,
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regval);
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*data |= (regval & 0xff) << 8;
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REG_READ(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_CMD_3,
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regval);
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*data |= (regval & 0xff) << 16;
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REG_READ(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_CMD_4,
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regval);
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*data |= (regval & 0xff) << 24;
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}
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PRIVATE void
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ixEthAccMdioStatusRead(UINT32 *data)
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{
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UINT32 regval;
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REG_READ(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_STS_1,
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regval);
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*data = regval & 0xff;
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REG_READ(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_STS_2,
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regval);
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*data |= (regval & 0xff) << 8;
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REG_READ(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_STS_3,
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regval);
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*data |= (regval & 0xff) << 16;
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REG_READ(miiBaseAddressVirt,
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IX_ETH_ACC_MAC_MDIO_STS_4,
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regval);
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*data |= (regval & 0xff) << 24;
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}
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/********************************************************************
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* ixEthAccMiiInit
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*/
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IxEthAccStatus
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ixEthAccMiiInit()
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{
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if(ixOsalMutexInit(&miiAccessLock)!= IX_SUCCESS)
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{
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return IX_ETH_ACC_FAIL;
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}
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miiBaseAddressVirt = (UINT32) IX_OSAL_MEM_MAP(IX_ETH_ACC_MAC_0_BASE, IX_OSAL_IXP400_ETHA_MAP_SIZE);
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if (miiBaseAddressVirt == 0)
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{
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ixOsalLog(IX_OSAL_LOG_LVL_FATAL,
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IX_OSAL_LOG_DEV_STDOUT,
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"EthAcc: Could not map MII I/O mapped memory\n",
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0, 0, 0, 0, 0, 0);
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return IX_ETH_ACC_FAIL;
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}
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return IX_ETH_ACC_SUCCESS;
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}
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void
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ixEthAccMiiUnload(void)
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{
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IX_OSAL_MEM_UNMAP(miiBaseAddressVirt);
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miiBaseAddressVirt = 0;
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}
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PUBLIC IxEthAccStatus
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ixEthAccMiiAccessTimeoutSet(UINT32 timeout, UINT32 retryCount)
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{
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if (retryCount < 1) return IX_ETH_ACC_FAIL;
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ixEthAccMiiRetryCount = retryCount;
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ixEthAccMiiAccessTimeout = timeout;
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return IX_ETH_ACC_SUCCESS;
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}
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/*********************************************************************
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* ixEthAccMiiReadRtn - read a 16 bit value from a PHY
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*/
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IxEthAccStatus
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ixEthAccMiiReadRtn (UINT8 phyAddr,
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UINT8 phyReg,
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UINT16 *value)
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{
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UINT32 mdioCommand;
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UINT32 regval;
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UINT32 miiTimeout;
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if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
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{
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return (IX_ETH_ACC_FAIL);
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}
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if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
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|| (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
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{
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return (IX_ETH_ACC_FAIL);
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}
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if (value == NULL)
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{
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return (IX_ETH_ACC_FAIL);
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}
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ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
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mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
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| phyAddr << IX_ETH_ACC_MII_ADDR_SHL;
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mdioCommand |= IX_ETH_ACC_MII_GO;
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ixEthAccMdioCmdWrite(mdioCommand);
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miiTimeout = ixEthAccMiiRetryCount;
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while(miiTimeout)
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{
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ixEthAccMdioCmdRead(®val);
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if((regval & IX_ETH_ACC_MII_GO) == 0x0)
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{
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break;
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}
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/* Sleep for a while */
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ixOsalSleep(ixEthAccMiiAccessTimeout);
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miiTimeout--;
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}
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if(miiTimeout == 0)
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{
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ixOsalMutexUnlock(&miiAccessLock);
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*value = 0xffff;
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return IX_ETH_ACC_FAIL;
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}
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ixEthAccMdioStatusRead(®val);
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if(regval & IX_ETH_ACC_MII_READ_FAIL)
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{
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ixOsalMutexUnlock(&miiAccessLock);
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*value = 0xffff;
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return IX_ETH_ACC_FAIL;
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}
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*value = regval & 0xffff;
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ixOsalMutexUnlock(&miiAccessLock);
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return IX_ETH_ACC_SUCCESS;
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}
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/*********************************************************************
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* ixEthAccMiiWriteRtn - write a 16 bit value to a PHY
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*/
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IxEthAccStatus
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ixEthAccMiiWriteRtn (UINT8 phyAddr,
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UINT8 phyReg,
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UINT16 value)
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{
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UINT32 mdioCommand;
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UINT32 regval;
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UINT16 readVal;
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UINT32 miiTimeout;
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if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
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{
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return (IX_ETH_ACC_FAIL);
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}
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if ((phyAddr >= IXP425_ETH_ACC_MII_MAX_ADDR)
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|| (phyReg >= IXP425_ETH_ACC_MII_MAX_REG))
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{
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return (IX_ETH_ACC_FAIL);
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}
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/* ensure that a PHY is present at this address */
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if(ixEthAccMiiReadRtn(phyAddr,
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IX_ETH_ACC_MII_CTRL_REG,
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&readVal) != IX_ETH_ACC_SUCCESS)
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{
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return (IX_ETH_ACC_FAIL);
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}
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ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
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mdioCommand = phyReg << IX_ETH_ACC_MII_REG_SHL
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| phyAddr << IX_ETH_ACC_MII_ADDR_SHL ;
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mdioCommand |= IX_ETH_ACC_MII_GO | IX_ETH_ACC_MII_WRITE | value;
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ixEthAccMdioCmdWrite(mdioCommand);
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miiTimeout = ixEthAccMiiRetryCount;
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while(miiTimeout)
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{
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ixEthAccMdioCmdRead(®val);
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/*The "GO" bit is reset to 0 when the write completes*/
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if((regval & IX_ETH_ACC_MII_GO) == 0x0)
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{
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break;
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}
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/* Sleep for a while */
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ixOsalSleep(ixEthAccMiiAccessTimeout);
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miiTimeout--;
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}
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ixOsalMutexUnlock(&miiAccessLock);
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if(miiTimeout == 0)
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{
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return IX_ETH_ACC_FAIL;
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}
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return IX_ETH_ACC_SUCCESS;
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}
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/*****************************************************************
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*
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* Phy query functions
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*
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*/
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IxEthAccStatus
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ixEthAccMiiStatsShow (UINT32 phyAddr)
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{
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UINT16 regval;
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printf("Regisers on PHY at address 0x%x\n", phyAddr);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_CTRL_REG, ®val);
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printf(" Control Register : 0x%4.4x\n", regval);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_STAT_REG, ®val);
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printf(" Status Register : 0x%4.4x\n", regval);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID1_REG, ®val);
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printf(" PHY ID1 Register : 0x%4.4x\n", regval);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_PHY_ID2_REG, ®val);
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printf(" PHY ID2 Register : 0x%4.4x\n", regval);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_ADS_REG, ®val);
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printf(" Auto Neg ADS Register : 0x%4.4x\n", regval);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_PRTN_REG, ®val);
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printf(" Auto Neg Partner Ability Register : 0x%4.4x\n", regval);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_EXP_REG, ®val);
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printf(" Auto Neg Expansion Register : 0x%4.4x\n", regval);
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ixEthAccMiiReadRtn(phyAddr, IX_ETH_ACC_MII_AN_NEXT_REG, ®val);
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printf(" Auto Neg Next Register : 0x%4.4x\n", regval);
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return IX_ETH_ACC_SUCCESS;
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}
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/*****************************************************************
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*
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* Interface query functions
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*
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*/
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IxEthAccStatus
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ixEthAccMdioShow (void)
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{
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UINT32 regval;
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if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())
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{
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return (IX_ETH_ACC_FAIL);
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}
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ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
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ixEthAccMdioCmdRead(®val);
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ixOsalMutexUnlock(&miiAccessLock);
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printf("MDIO command register\n");
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printf(" Go bit : 0x%x\n", (regval & BIT(31)) >> 31);
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printf(" MDIO Write : 0x%x\n", (regval & BIT(26)) >> 26);
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printf(" PHY address : 0x%x\n", (regval >> 21) & 0x1f);
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printf(" Reg address : 0x%x\n", (regval >> 16) & 0x1f);
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ixOsalMutexLock(&miiAccessLock, IX_OSAL_WAIT_FOREVER);
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ixEthAccMdioStatusRead(®val);
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ixOsalMutexUnlock(&miiAccessLock);
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printf("MDIO status register\n");
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printf(" Read OK : 0x%x\n", (regval & BIT(31)) >> 31);
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printf(" Read Data : 0x%x\n", (regval >> 16) & 0xff);
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return IX_ETH_ACC_SUCCESS;
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}
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