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https://github.com/smaeul/u-boot.git
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1d457dbb91
Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED Signed-off-by: Tom Rini <trini@konsulko.com>
153 lines
4.6 KiB
C
153 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007-2013 Tensilica, Inc.
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* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/core.h>
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#include <asm/addrspace.h>
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#include <asm/config.h>
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/*
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* The 'xtfpga' board describes a set of very similar boards with only minimal
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* differences.
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*/
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/*===================*/
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/* RAM Layout */
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/*===================*/
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#if XCHAL_HAVE_PTP_MMU
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#define CFG_SYS_MEMORY_BASE \
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(XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR)
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#define CFG_SYS_IO_BASE 0xf0000000
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#else
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#define CFG_SYS_MEMORY_BASE 0x60000000
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#define CFG_SYS_IO_BASE 0x90000000
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#define CFG_MAX_MEM_MAPPED 0x10000000
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#endif
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/* Onboard RAM sizes:
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*
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* LX60 0x04000000 64 MB
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* LX110 0x03000000 48 MB
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* LX200 0x06000000 96 MB
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* ML605 0x18000000 384 MB
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* KC705 0x38000000 896 MB
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*
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* noMMU configurations can only see first 256MB of onboard memory.
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*/
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#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000
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#define CFG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE
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#else
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#define CFG_SYS_SDRAM_SIZE 0x10000000
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#endif
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#define CFG_SYS_SDRAM_BASE MEMADDR(0x00000000)
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/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */
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/* Memory test is destructive so default must not overlap vectors or U-Boot*/
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#if defined(CFG_MAX_MEM_MAPPED) && \
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CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE
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#define XTENSA_SYS_TEXT_ADDR \
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(MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
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#else
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#define XTENSA_SYS_TEXT_ADDR \
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(MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)
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#endif
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/*==============================*/
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/* U-Boot general configuration */
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/*==============================*/
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/* Console I/O Buffer Size */
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/*==============================*/
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/* U-Boot autoboot configuration */
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/*==============================*/
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/*=========================================*/
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/* FPGA Registers (board info and control) */
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/*=========================================*/
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/*
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* These assume FPGA bitstreams from Tensilica release RB and up. Earlier
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* releases may not provide any/all of these registers or at these offsets.
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* Some of the FPGA registers are broken down into bitfields described by
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* SHIFT left amount and field WIDTH (bits), and also by a bitMASK.
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*/
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/* FPGA core clock frequency in Hz (also input to UART) */
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#define CFG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/
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/*
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* DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1):
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* Bits 0..5 set the lower 6 bits of the default ethernet MAC.
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* Bit 6 is reserved for future use by Tensilica.
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* Bit 7 maps the first 128KB of ROM address space at CFG_SYS_ROM_BASE to
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* the base of flash * (when on/1) or to the base of RAM (when off/0).
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*/
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#define CFG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C)
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#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */
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#define FPGAREG_MAC_WIDTH 6
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#define FPGAREG_MAC_MASK 0x3f
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#define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */
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#define FPGAREG_BOOT_WIDTH 1
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#define FPGAREG_BOOT_MASK 0x80
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#define FPGAREG_BOOT_RAM 0
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#define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT)
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/* Force hard reset of board by writing a code to this register */
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#define CFG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */
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#define CFG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */
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/*====================*/
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/* Serial Driver Info */
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/*====================*/
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#define CFG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */
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/* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */
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#define CFG_SYS_NS16550_CLK get_board_sys_clk()
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/*======================*/
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/* Ethernet Driver Info */
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/*======================*/
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#define CFG_ETHBASE 00:50:C2:13:6f:00
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#define CFG_SYS_ETHOC_BASE IOADDR(0x0d030000)
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#define CFG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000)
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/*=====================*/
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/* Flash & Environment */
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/*=====================*/
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#ifdef CONFIG_XTFPGA_LX60
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# define CFG_SYS_FLASH_SIZE 0x0040000 /* 4MB */
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# define CFG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */
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# define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
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#elif defined(CONFIG_XTFPGA_KC705)
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# define CFG_SYS_FLASH_SIZE 0x8000000 /* 128MB */
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# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
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# define CFG_SYS_FLASH_BASE IOADDR(0x00000000)
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#else
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# define CFG_SYS_FLASH_SIZE 0x1000000 /* 16MB */
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# define CFG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */
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# define CFG_SYS_FLASH_BASE IOADDR(0x08000000)
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#endif
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/*
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* Put environment in top block (64kB)
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* Another option would be to put env. in 2nd param block offs 8KB, size 8KB
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*/
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/* print 'E' for empty sector on flinfo */
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#endif /* __CONFIG_H */
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