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cdaa69c46e
Init GICv3 for V3U Falcon in early phase Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
102 lines
2.1 KiB
C
102 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/renesas/falcon/falcon.c
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* This file is Falcon board support.
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#include <common.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/processor.h>
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#include <linux/errno.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPR 0xE6150000
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#define CPGWPCR 0xE6150004
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#define EXTAL_CLK 16666600u
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#define CNTCR_BASE 0xE6080000
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#define CNTFID0 (CNTCR_BASE + 0x020)
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#define CNTCR_EN BIT(0)
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static void init_generic_timer(void)
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{
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u32 freq;
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/* Set frequency data in CNTFID0 */
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freq = EXTAL_CLK;
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/* Update memory mapped and register based freqency */
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asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
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writel(freq, CNTFID0);
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/* Enable counter */
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setbits_le32(CNTCR_BASE, CNTCR_EN);
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}
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/* Distributor Registers */
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#define GICD_BASE 0xF1000000
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/* ReDistributor Registers for Control and Physical LPIs */
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#define GICR_LPI_BASE 0xF1060000
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#define GICR_WAKER 0x0014
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#define GICR_PWRR 0x0024
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#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
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#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR)
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/* ReDistributor Registers for SGIs and PPIs */
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#define GICR_SGI_BASE 0xF1070000
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#define GICR_IGROUPR0 0x0080
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static void init_gic_v3(void)
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{
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/* GIC v3 power on */
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writel(0x00000002, (GICR_LPI_PWRR));
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/* Wait till the WAKER_CA_BIT changes to 0 */
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writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER));
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while (readl(GICR_LPI_WAKER) & 0x00000004)
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;
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writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
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}
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void s_init(void)
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{
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init_generic_timer();
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}
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int board_early_init_f(void)
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{
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/* Unlock CPG access */
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
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init_gic_v3();
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return 0;
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}
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#define RST_BASE 0xE6160000 /* Domain0 */
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#define RST_SRESCR0 (RST_BASE + 0x18)
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#define RST_SPRES 0x5AA58000
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void reset_cpu(void)
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{
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writel(RST_SPRES, RST_SRESCR0);
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}
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