mirror of
https://github.com/smaeul/u-boot.git
synced 2025-11-04 05:50:17 +00:00
da634ae356
With uppcoming BCH support on OMAP devices we need to decide between differnt algorithms when switching the ECC engine. Currently we support 1-bit hammign and 8-bit BCH on HW backend. In order to switch between differnet ECC algorithms we need to change the interface of omap_nand_switch_ecc() also. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Tom Rini <trini@ti.com> Cc: Thomas Weber <thomas.weber.linux@googlemail.com>
88 lines
2.3 KiB
C
88 lines
2.3 KiB
C
/*
|
|
* (C) Copyright 2004-2008
|
|
* Texas Instruments, <www.ti.com>
|
|
* Richard Woodruff <r-woodruff2@ti.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
#ifndef _SYS_PROTO_H_
|
|
#define _SYS_PROTO_H_
|
|
|
|
typedef struct {
|
|
u32 mtype;
|
|
char *board_string;
|
|
char *nand_string;
|
|
} omap3_sysinfo;
|
|
|
|
struct emu_hal_params {
|
|
u32 num_params;
|
|
u32 param1;
|
|
};
|
|
|
|
/* Board SDRC timing values */
|
|
struct board_sdrc_timings {
|
|
u32 mcfg;
|
|
u32 ctrla;
|
|
u32 ctrlb;
|
|
u32 rfr_ctrl;
|
|
u32 mr;
|
|
};
|
|
|
|
void prcm_init(void);
|
|
void per_clocks_enable(void);
|
|
void ehci_clocks_enable(void);
|
|
|
|
void memif_init(void);
|
|
void sdrc_init(void);
|
|
void do_sdrc_init(u32, u32);
|
|
|
|
void get_board_mem_timings(struct board_sdrc_timings *timings);
|
|
void identify_nand_chip(int *mfr, int *id);
|
|
void emif4_init(void);
|
|
void gpmc_init(void);
|
|
void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
|
|
u32 size);
|
|
|
|
void watchdog_init(void);
|
|
void set_muxconf_regs(void);
|
|
|
|
u32 get_cpu_family(void);
|
|
u32 get_cpu_rev(void);
|
|
u32 get_sku_id(void);
|
|
u32 get_sysboot_value(void);
|
|
u32 is_gpmc_muxed(void);
|
|
u32 get_gpmc0_type(void);
|
|
u32 get_gpmc0_width(void);
|
|
u32 is_running_in_sdram(void);
|
|
u32 is_running_in_sram(void);
|
|
u32 is_running_in_flash(void);
|
|
u32 get_device_type(void);
|
|
void secureworld_exit(void);
|
|
void try_unlock_memory(void);
|
|
u32 get_boot_type(void);
|
|
void invalidate_dcache(u32);
|
|
void sr32(void *, u32, u32, u32);
|
|
u32 wait_on_value(u32, u32, void *, u32);
|
|
void sdelay(unsigned long);
|
|
void make_cs1_contiguous(void);
|
|
void omap_nand_switch_ecc(uint32_t, uint32_t);
|
|
void power_init_r(void);
|
|
void dieid_num_r(void);
|
|
void do_omap3_emu_romcode_call(u32 service_id, u32 parameters);
|
|
void omap3_gp_romcode_call(u32 service_id, u32 parameter);
|
|
u32 warm_reset(void);
|
|
#endif
|