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b80e41ac54
Adds support for the ARM quad-core Cortex-A9 processor This system includes a motherboard(Versatile Express), daughterboard (Coretile), and SOC(Cortex-A9 quad core). The serial port, ethernet, and flash systems work with these additions. The naming convention is: SOC -> CortexA9 quad core = ca9x4 daughterboard -> Coretile = ct motherboard -> Versatile Express = vxp This gives ca9x4_ct_vxp.c as the board support file. Signed-off-by: Matt Waddel <matt.waddel@linaro.org>
51 lines
1.4 KiB
C
51 lines
1.4 KiB
C
/*
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* (C) Copyright 2010 Linaro
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* Matt Waddel, <matt.waddel@linaro.org>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SYSTIMER_H_
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#define _SYSTIMER_H_
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/* AMBA timer register base address */
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#define SYSTIMER_BASE 0x10011000
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#define SYSHZ_CLOCK 1000000 /* Timers -> 1Mhz */
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#define SYSTIMER_RELOAD 0xFFFFFFFF
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#define SYSTIMER_EN (1 << 7)
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#define SYSTIMER_32BIT (1 << 1)
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struct systimer {
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u32 timer0load; /* 0x00 */
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u32 timer0value;
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u32 timer0control;
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u32 timer0intclr;
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u32 timer0ris;
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u32 timer0mis;
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u32 timer0bgload;
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u32 timer1load; /* 0x20 */
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u32 timer1value;
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u32 timer1control;
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u32 timer1intclr;
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u32 timer1ris;
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u32 timer1mis;
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u32 timer1bgload;
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};
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#endif /* _SYSTIMER_H_ */
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