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b36df56115
This patch moves some ppc4xx related headers from the common include directory (include/) to the powerpc specific one (arch/powerpc/include/asm/). This way to common include directory is not so cluttered with files. Signed-off-by: Stefan Roese <sr@denx.de>
465 lines
12 KiB
C
465 lines
12 KiB
C
/*
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* arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c
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* This SPD SDRAM detection code supports IBM/AMCC PPC44x cpu with a
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* SDRAM controller. Those are all current 405 PPC's.
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*
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* (C) Copyright 2001
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* Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
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*
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* Based on code by:
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*
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* Kenneth Johansson ,Ericsson AB.
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* kenneth.johansson@etx.ericsson.se
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*
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* hacked up by bill hunter. fixed so we could run before
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* serial_init and console_init. previous version avoided this by
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* running out of cache memory during serial/console init, then running
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* this code later.
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*
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* (C) Copyright 2002
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* Jun Gu, Artesyn Technology, jung@artesyncp.com
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* Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
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*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <asm/ppc4xx.h>
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#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440)
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/*
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* Set default values
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*/
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#ifndef CONFIG_SYS_I2C_SPEED
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#define CONFIG_SYS_I2C_SPEED 50000
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#endif
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#define ONE_BILLION 1000000000
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#define SDRAM0_CFG_DCE 0x80000000
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#define SDRAM0_CFG_SRE 0x40000000
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#define SDRAM0_CFG_PME 0x20000000
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#define SDRAM0_CFG_MEMCHK 0x10000000
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#define SDRAM0_CFG_REGEN 0x08000000
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#define SDRAM0_CFG_ECCDD 0x00400000
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#define SDRAM0_CFG_EMDULR 0x00200000
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#define SDRAM0_CFG_DRW_SHIFT (31-6)
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#define SDRAM0_CFG_BRPF_SHIFT (31-8)
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#define SDRAM0_TR_CASL_SHIFT (31-8)
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#define SDRAM0_TR_PTA_SHIFT (31-13)
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#define SDRAM0_TR_CTP_SHIFT (31-15)
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#define SDRAM0_TR_LDF_SHIFT (31-17)
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#define SDRAM0_TR_RFTA_SHIFT (31-29)
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#define SDRAM0_TR_RCD_SHIFT (31-31)
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#define SDRAM0_RTR_SHIFT (31-15)
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#define SDRAM0_ECCCFG_SHIFT (31-11)
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/* SDRAM0_CFG enable macro */
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#define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
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#define SDRAM0_BXCR_SZ_MASK 0x000e0000
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#define SDRAM0_BXCR_AM_MASK 0x0000e000
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#define SDRAM0_BXCR_SZ_SHIFT (31-14)
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#define SDRAM0_BXCR_AM_SHIFT (31-18)
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#define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
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#define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
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#ifdef CONFIG_SPDDRAM_SILENT
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# define SPD_ERR(x) do { return 0; } while (0)
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#else
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# define SPD_ERR(x) do { printf(x); return(0); } while (0)
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#endif
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#define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
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/* function prototypes */
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int spd_read(uint addr);
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/*
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* This function is reading data from the DIMM module EEPROM over the SPD bus
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* and uses that to program the sdram controller.
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*
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* This works on boards that has the same schematics that the AMCC walnut has.
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*
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* Input: null for default I2C spd functions or a pointer to a custom function
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* returning spd_data.
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*/
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long int spd_sdram(int(read_spd)(uint addr))
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{
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int tmp,row,col;
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int total_size,bank_size,bank_code;
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int ecc_on;
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int mode;
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int bank_cnt;
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int sdram0_pmit=0x07c00000;
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#ifndef CONFIG_405EP /* not on PPC405EP */
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int sdram0_besr0 = -1;
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int sdram0_besr1 = -1;
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int sdram0_eccesr = -1;
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#endif
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int sdram0_ecccfg;
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int sdram0_rtr=0;
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int sdram0_tr=0;
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int sdram0_b0cr;
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int sdram0_b1cr;
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int sdram0_b2cr;
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int sdram0_b3cr;
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int sdram0_cfg=0;
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int t_rp;
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int t_rcd;
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int t_ras;
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int t_rc;
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int min_cas;
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PPC4xx_SYS_INFO sys_info;
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unsigned long bus_period_x_10;
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/*
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* get the board info
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*/
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get_sys_info(&sys_info);
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bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
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if (read_spd == 0){
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read_spd=spd_read;
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/*
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* Make sure I2C controller is initialized
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* before continuing.
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*/
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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}
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/* Make shure we are using SDRAM */
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if (read_spd(2) != 0x04) {
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SPD_ERR("SDRAM - non SDRAM memory module found\n");
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}
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/* ------------------------------------------------------------------
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* configure memory timing register
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*
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* data from DIMM:
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* 27 IN Row Precharge Time ( t RP)
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* 29 MIN RAS to CAS Delay ( t RCD)
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* 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
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* -------------------------------------------------------------------*/
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/*
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* first figure out which cas latency mode to use
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* use the min supported mode
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*/
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tmp = read_spd(127) & 0x6;
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if (tmp == 0x02) { /* only cas = 2 supported */
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min_cas = 2;
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/* t_ck = read_spd(9); */
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/* t_ac = read_spd(10); */
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} else if (tmp == 0x04) { /* only cas = 3 supported */
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min_cas = 3;
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/* t_ck = read_spd(9); */
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/* t_ac = read_spd(10); */
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} else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
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min_cas = 2;
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/* t_ck = read_spd(23); */
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/* t_ac = read_spd(24); */
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} else {
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SPD_ERR("SDRAM - unsupported CAS latency \n");
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}
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/* get some timing values, t_rp,t_rcd,t_ras,t_rc
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*/
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t_rp = read_spd(27);
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t_rcd = read_spd(29);
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t_ras = read_spd(30);
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t_rc = t_ras + t_rp;
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/* The following timing calcs subtract 1 before deviding.
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* this has effect of using ceiling instead of floor rounding,
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* and also subtracting 1 to convert number to reg value
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*/
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/* set up CASL */
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sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
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/* set up PTA */
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sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
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/* set up CTP */
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tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
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if (tmp < 1)
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tmp = 1;
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sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
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/* set LDF = 2 cycles, reg value = 1 */
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sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
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/* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
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tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
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if (tmp < 0)
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tmp = 0;
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if (tmp > 6)
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tmp = 6;
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sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
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/* set RCD = t_rcd/bus_period*/
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sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
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/*------------------------------------------------------------------
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* configure RTR register
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* -------------------------------------------------------------------*/
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row = read_spd(3);
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col = read_spd(4);
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tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
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switch (tmp) {
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case 0x00:
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tmp = 15625;
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break;
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case 0x01:
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tmp = 15625 / 4;
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break;
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case 0x02:
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tmp = 15625 / 2;
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break;
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case 0x03:
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tmp = 15625 * 2;
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break;
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case 0x04:
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tmp = 15625 * 4;
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break;
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case 0x05:
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tmp = 15625 * 8;
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break;
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default:
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SPD_ERR("SDRAM - Bad refresh period \n");
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}
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/* convert from nsec to bus cycles */
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tmp = (tmp * 10) / bus_period_x_10;
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sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
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/*------------------------------------------------------------------
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* determine the number of banks used
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* -------------------------------------------------------------------*/
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/* byte 7:6 is module data width */
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if (read_spd(7) != 0)
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SPD_ERR("SDRAM - unsupported module width\n");
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tmp = read_spd(6);
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if (tmp < 32)
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SPD_ERR("SDRAM - unsupported module width\n");
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else if (tmp < 64)
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bank_cnt = 1; /* one bank per sdram side */
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else if (tmp < 73)
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bank_cnt = 2; /* need two banks per side */
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else if (tmp < 161)
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bank_cnt = 4; /* need four banks per side */
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else
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SPD_ERR("SDRAM - unsupported module width\n");
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/* byte 5 is the module row count (refered to as dimm "sides") */
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tmp = read_spd(5);
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if (tmp == 1)
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;
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else if (tmp==2)
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bank_cnt *= 2;
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else if (tmp==4)
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bank_cnt *= 4;
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else
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bank_cnt = 8; /* 8 is an error code */
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if (bank_cnt > 4) /* we only have 4 banks to work with */
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SPD_ERR("SDRAM - unsupported module rows for this width\n");
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/* now check for ECC ability of module. We only support ECC
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* on 32 bit wide devices with 8 bit ECC.
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*/
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if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
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sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
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ecc_on = 1;
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} else {
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sdram0_ecccfg = 0;
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ecc_on = 0;
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}
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/*------------------------------------------------------------------
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* calculate total size
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* -------------------------------------------------------------------*/
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/* calculate total size and do sanity check */
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tmp = read_spd(31);
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total_size = 1 << 22; /* total_size = 4MB */
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/* now multiply 4M by the smallest device row density */
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/* note that we don't support asymetric rows */
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while (((tmp & 0x0001) == 0) && (tmp != 0)) {
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total_size = total_size << 1;
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tmp = tmp >> 1;
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}
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total_size *= read_spd(5); /* mult by module rows (dimm sides) */
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/*------------------------------------------------------------------
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* map rows * cols * banks to a mode
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* -------------------------------------------------------------------*/
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switch (row) {
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case 11:
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switch (col) {
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case 8:
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mode=4; /* mode 5 */
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break;
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case 9:
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case 10:
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mode=0; /* mode 1 */
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break;
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default:
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SPD_ERR("SDRAM - unsupported mode\n");
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}
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break;
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case 12:
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switch (col) {
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case 8:
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mode=3; /* mode 4 */
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break;
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case 9:
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case 10:
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mode=1; /* mode 2 */
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break;
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default:
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SPD_ERR("SDRAM - unsupported mode\n");
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}
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break;
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case 13:
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switch (col) {
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case 8:
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mode=5; /* mode 6 */
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break;
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case 9:
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case 10:
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if (read_spd(17) == 2)
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mode = 6; /* mode 7 */
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else
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mode = 2; /* mode 3 */
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break;
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case 11:
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mode = 2; /* mode 3 */
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break;
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default:
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SPD_ERR("SDRAM - unsupported mode\n");
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}
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break;
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default:
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SPD_ERR("SDRAM - unsupported mode\n");
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}
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/*------------------------------------------------------------------
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* using the calculated values, compute the bank
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* config register values.
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* -------------------------------------------------------------------*/
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sdram0_b1cr = 0;
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sdram0_b2cr = 0;
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sdram0_b3cr = 0;
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/* compute the size of each bank */
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bank_size = total_size / bank_cnt;
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/* convert bank size to bank size code for ppc4xx
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by takeing log2(bank_size) - 22 */
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tmp = bank_size; /* start with tmp = bank_size */
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bank_code = 0; /* and bank_code = 0 */
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while (tmp > 1) { /* this takes log2 of tmp */
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bank_code++; /* and stores result in bank_code */
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tmp = tmp >> 1;
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} /* bank_code is now log2(bank_size) */
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bank_code -= 22; /* subtract 22 to get the code */
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tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
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sdram0_b0cr = (bank_size * 0) | tmp;
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#ifndef CONFIG_405EP /* not on PPC405EP */
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if (bank_cnt > 1)
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sdram0_b2cr = (bank_size * 1) | tmp;
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if (bank_cnt > 2)
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sdram0_b1cr = (bank_size * 2) | tmp;
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if (bank_cnt > 3)
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sdram0_b3cr = (bank_size * 3) | tmp;
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#else
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/* PPC405EP chip only supports two SDRAM banks */
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if (bank_cnt > 1)
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sdram0_b1cr = (bank_size * 1) | tmp;
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if (bank_cnt > 2)
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total_size = 2 * bank_size;
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#endif
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/*
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* enable sdram controller DCE=1
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* enable burst read prefetch to 32 bytes BRPF=2
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* leave other functions off
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*/
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/*------------------------------------------------------------------
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* now that we've done our calculations, we are ready to
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* program all the registers.
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* -------------------------------------------------------------------*/
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/* disable memcontroller so updates work */
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mtsdram(SDRAM0_CFG, 0);
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#ifndef CONFIG_405EP /* not on PPC405EP */
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mtsdram(SDRAM0_BESR0, sdram0_besr0);
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mtsdram(SDRAM0_BESR1, sdram0_besr1);
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mtsdram(SDRAM0_ECCCFG, sdram0_ecccfg);
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mtsdram(SDRAM0_ECCESR, sdram0_eccesr);
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#endif
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mtsdram(SDRAM0_RTR, sdram0_rtr);
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mtsdram(SDRAM0_PMIT, sdram0_pmit);
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mtsdram(SDRAM0_B0CR, sdram0_b0cr);
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mtsdram(SDRAM0_B1CR, sdram0_b1cr);
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#ifndef CONFIG_405EP /* not on PPC405EP */
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mtsdram(SDRAM0_B2CR, sdram0_b2cr);
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mtsdram(SDRAM0_B3CR, sdram0_b3cr);
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#endif
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mtsdram(SDRAM0_TR, sdram0_tr);
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/* SDRAM have a power on delay, 500 micro should do */
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udelay(500);
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sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
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if (ecc_on)
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sdram0_cfg |= SDRAM0_CFG_MEMCHK;
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mtsdram(SDRAM0_CFG, sdram0_cfg);
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return (total_size);
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}
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int spd_read(uint addr)
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{
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uchar data[2];
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if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
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return (int)data[0];
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else
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return 0;
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}
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#endif /* CONFIG_SPD_EEPROM */
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