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f51cdaf191
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
/*
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* MPC8360E-RDK support for the NAND on FSL UPM
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*
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* Copyright (C) 2007 MontaVista Software, Inc.
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* Anton Vorontsov <avorontsov@ru.mvista.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_83xx.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/fsl_upm.h>
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#include <nand.h>
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static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
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static const u32 upm_array[] = {
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0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words 0 to 3 */
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0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 4 to 7 */
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0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words 8 to 11 */
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0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */
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0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */
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0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */
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0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */
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0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */
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0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */
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0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */
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0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */
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0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */
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0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */
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};
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static void upm_setup(struct fsl_upm *upm)
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{
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int i;
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/* write upm array */
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out_be32(upm->mxmr, MxMR_OP_WARR);
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for (i = 0; i < 64; i++) {
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out_be32(upm->mdr, upm_array[i]);
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out_8(upm->io_addr, 0x0);
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}
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/* normal operation */
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out_be32(upm->mxmr, MxMR_OP_NORM);
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while (in_be32(upm->mxmr) != MxMR_OP_NORM)
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eieio();
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}
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static int dev_ready(int chip_nr)
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{
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if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
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debug("nand ready\n");
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return 1;
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}
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debug("nand busy\n");
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return 0;
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}
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static struct fsl_upm_nand fun = {
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.upm = {
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.io_addr = (void *)CONFIG_SYS_NAND_BASE,
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},
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.width = 8,
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.upm_cmd_offset = 8,
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.upm_addr_offset = 16,
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.dev_ready = dev_ready,
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.wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
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.chip_delay = 50,
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};
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int board_nand_init(struct nand_chip *nand)
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{
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fun.upm.mxmr = &im->im_lbc.mamr;
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fun.upm.mdr = &im->im_lbc.mdr;
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fun.upm.mar = &im->im_lbc.mar;
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upm_setup(&fun.upm);
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return fsl_upm_nand_init(nand, &fun);
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}
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