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6261cf6abd
When building with AARCH64 defconfig, we got warnings, fix them by using registers base address defined as void __iomem * instead of fdt_addr_t. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
84 lines
2.0 KiB
C
84 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#ifndef _SERIAL_STM32_
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#define _SERIAL_STM32_
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#include <linux/bitops.h>
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#define CR1_OFFSET(x) (x ? 0x0c : 0x00)
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#define CR3_OFFSET(x) (x ? 0x14 : 0x08)
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#define BRR_OFFSET(x) (x ? 0x08 : 0x0c)
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#define ISR_OFFSET(x) (x ? 0x00 : 0x1c)
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#define ICR_OFFSET 0x20
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/*
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* STM32F4 has one Data Register (DR) for received or transmitted
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* data, so map Receive Data Register (RDR) and Transmit Data
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* Register (TDR) at the same offset
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*/
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#define RDR_OFFSET(x) (x ? 0x04 : 0x24)
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#define TDR_OFFSET(x) (x ? 0x04 : 0x28)
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struct stm32_uart_info {
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u8 uart_enable_bit; /* UART_CR1_UE */
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bool stm32f4; /* true for STM32F4, false otherwise */
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bool has_fifo;
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};
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struct stm32_uart_info stm32f4_info = {
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.stm32f4 = true,
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.uart_enable_bit = 13,
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.has_fifo = false,
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};
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struct stm32_uart_info stm32f7_info = {
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.uart_enable_bit = 0,
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.stm32f4 = false,
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.has_fifo = true,
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};
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struct stm32_uart_info stm32h7_info = {
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.uart_enable_bit = 0,
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.stm32f4 = false,
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.has_fifo = true,
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};
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/* Information about a serial port */
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struct stm32x7_serial_plat {
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void __iomem *base; /* address of registers in physical memory */
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struct stm32_uart_info *uart_info;
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unsigned long int clock_rate;
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};
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#define USART_CR1_FIFOEN BIT(29)
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#define USART_CR1_M1 BIT(28)
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#define USART_CR1_OVER8 BIT(15)
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#define USART_CR1_M0 BIT(12)
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#define USART_CR1_PCE BIT(10)
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#define USART_CR1_PS BIT(9)
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#define USART_CR1_TE BIT(3)
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#define USART_CR1_RE BIT(2)
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#define USART_CR3_OVRDIS BIT(12)
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#define USART_ISR_TXE BIT(7)
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#define USART_ISR_TC BIT(6)
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#define USART_ISR_RXNE BIT(5)
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#define USART_ISR_ORE BIT(3)
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#define USART_ISR_FE BIT(1)
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#define USART_ISR_PE BIT(0)
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#define USART_BRR_F_MASK GENMASK(7, 0)
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#define USART_BRR_M_SHIFT 4
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#define USART_BRR_M_MASK GENMASK(15, 4)
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#define USART_ICR_ORECF BIT(3)
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#define USART_ICR_FECF BIT(1)
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#define USART_ICR_PCECF BIT(0)
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#endif
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