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fe1b4db05e
This patch adds the basic pinmux and gpio support for the Allwinner A20 (sun7i) processor. This code will not been compiled until the build is hooked up in a later patch. It has been split out to keep the patches manageable. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Ma Haijun <mahaijuns@gmail.com> Signed-off-by: Oliver Schinagl <oliver@schinagl.nl> Signed-off-by: Henrik Nordström <henrik@henriknordstrom.net> Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Tom Rini <trini@ti.com> Acked-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Tom Cubie <Mr.hipboi@gmail.com> Reviewed-by: Tom Rini <trini@ti.com>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
/*
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* (C) Copyright 2007-2011
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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int sunxi_gpio_set_cfgpin(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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u32 index = GPIO_CFG_INDEX(pin);
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u32 offset = GPIO_CFG_OFFSET(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset);
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return 0;
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}
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int sunxi_gpio_get_cfgpin(u32 pin)
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{
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u32 cfg;
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u32 bank = GPIO_BANK(pin);
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u32 index = GPIO_CFG_INDEX(pin);
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u32 offset = GPIO_CFG_OFFSET(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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cfg = readl(&pio->cfg[0] + index);
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cfg >>= offset;
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return cfg & 0xf;
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}
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int sunxi_gpio_set_drv(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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u32 index = GPIO_DRV_INDEX(pin);
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u32 offset = GPIO_DRV_OFFSET(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset);
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return 0;
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}
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int sunxi_gpio_set_pull(u32 pin, u32 val)
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{
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u32 bank = GPIO_BANK(pin);
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u32 index = GPIO_PULL_INDEX(pin);
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u32 offset = GPIO_PULL_OFFSET(pin);
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struct sunxi_gpio *pio = BANK_TO_GPIO(bank);
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clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset);
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return 0;
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}
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