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	Add a flag to set ahb/apb/fiu/spi clock divider as read-only The spi clock setting is related to booting flash, it is setup by early bootloader. It just protects the clock source and can't modify it in uboot. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Link: https://lore.kernel.org/r/20231114090004.3746024-1-JJLIU0@nuvoton.com
		
			
				
	
	
		
			309 lines
		
	
	
		
			6.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			309 lines
		
	
	
		
			6.5 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| // SPDX-License-Identifier: GPL-2.0+
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| /*
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|  * Copyright (c) 2022 Nuvoton Technology Corp.
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|  *
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|  * Formula for calculating clock rate:
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|  * Fout = ((Fin / PRE_DIV) / div) / POST_DIV
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|  */
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| 
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| #include <div64.h>
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| #include <dm.h>
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| #include <asm/io.h>
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| #include <linux/bitfield.h>
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| #include <linux/log2.h>
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| #include "clk_npcm.h"
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| 
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| static int clkid_to_clksel(struct npcm_clk_select *selector, int id)
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| {
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| 	int i;
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| 
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| 	for (i = 0; i < selector->num_parents; i++) {
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| 		if (selector->parents[i].id == id)
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| 			return selector->parents[i].clksel;
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| 	}
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| 
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| 	return -EINVAL;
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| }
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| 
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| static int clksel_to_clkid(struct npcm_clk_select *selector, int clksel)
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| {
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| 	int i;
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| 
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| 	for (i = 0; i < selector->num_parents; i++) {
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| 		if (selector->parents[i].clksel == clksel)
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| 			return selector->parents[i].id;
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| 	}
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| 
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| 	return -EINVAL;
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| }
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| 
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| static struct npcm_clk_pll *npcm_clk_pll_get(struct npcm_clk_data *clk_data, int id)
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| {
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| 	struct npcm_clk_pll *pll = clk_data->clk_plls;
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| 	int i;
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| 
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| 	for (i = 0; i < clk_data->num_plls; i++) {
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| 		if (pll->id == id)
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| 			return pll;
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| 		pll++;
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| 	}
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| 
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| 	return NULL;
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| }
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| 
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| static struct npcm_clk_select *npcm_clk_selector_get(struct npcm_clk_data *clk_data,
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| 						     int id)
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| {
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| 	struct npcm_clk_select *selector = clk_data->clk_selectors;
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| 	int i;
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| 
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| 	for (i = 0; i < clk_data->num_selectors; i++) {
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| 		if (selector->id == id)
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| 			return selector;
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| 		selector++;
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| 	}
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| 
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| 	return NULL;
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| }
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| 
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| static struct npcm_clk_div *npcm_clk_divider_get(struct npcm_clk_data *clk_data,
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| 						 int id)
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| {
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| 	struct npcm_clk_div *divider = clk_data->clk_dividers;
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| 	int i;
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| 
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| 	for (i = 0; i < clk_data->num_dividers; i++) {
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| 		if (divider->id == id)
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| 			return divider;
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| 		divider++;
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| 	}
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| 
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| 	return NULL;
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| }
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| 
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| static ulong npcm_clk_get_fin(struct clk *clk)
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| {
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| 	struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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| 	struct npcm_clk_select *selector;
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| 	struct clk parent;
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| 	ulong parent_rate;
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| 	u32 val, clksel;
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| 	int ret;
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| 
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| 	selector = npcm_clk_selector_get(priv->clk_data, clk->id);
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| 	if (!selector)
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| 		return 0;
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| 
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| 	if (selector->flags & FIXED_PARENT) {
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| 		clksel = 0;
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| 	} else {
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| 		val = readl(priv->base + selector->reg);
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| 		clksel = (val & selector->mask) >> (ffs(selector->mask) - 1);
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| 	}
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| 	parent.id = clksel_to_clkid(selector, clksel);
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| 
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| 	ret = clk_request(clk->dev, &parent);
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| 	if (ret)
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| 		return 0;
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| 
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| 	parent_rate = clk_get_rate(&parent);
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| 
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| 	debug("fin of clk%lu = %lu\n", clk->id, parent_rate);
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| 	return parent_rate;
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| }
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| 
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| static u32 npcm_clk_get_div(struct clk *clk)
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| {
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| 	struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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| 	struct npcm_clk_div *divider;
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| 	u32 val, div;
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| 
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| 	divider = npcm_clk_divider_get(priv->clk_data, clk->id);
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| 	if (!divider)
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| 		return 0;
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| 
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| 	val = readl(priv->base + divider->reg);
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| 	div = (val & divider->mask) >> (ffs(divider->mask) - 1);
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| 	if (divider->flags & DIV_TYPE1)
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| 		div = div + 1;
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| 	else
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| 		div = 1 << div;
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| 
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| 	if (divider->flags & PRE_DIV2)
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| 		div = div << 1;
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| 
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| 	return div;
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| }
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| 
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| static int npcm_clk_set_div(struct clk *clk, u32 div)
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| {
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| 	struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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| 	struct npcm_clk_div *divider;
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| 	u32 val, clkdiv;
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| 
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| 	divider = npcm_clk_divider_get(priv->clk_data, clk->id);
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| 	if (!divider)
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| 		return -EINVAL;
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| 
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| 	if (divider->flags & DIV_RO)
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| 		return 0;
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| 
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| 	if (divider->flags & PRE_DIV2)
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| 		div = div >> 1;
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| 
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| 	if (divider->flags & DIV_TYPE1)
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| 		clkdiv = div - 1;
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| 	else
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| 		clkdiv = ilog2(div);
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| 
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| 	if (clkdiv > (divider->mask >> (ffs(divider->mask) - 1))) {
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| 		printf("clkdiv(%d) for clk(%ld) is over limit\n",
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| 		       clkdiv, clk->id);
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| 		return -EINVAL;
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| 	}
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| 
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| 	val = readl(priv->base + divider->reg);
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| 	val &= ~divider->mask;
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| 	val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask;
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| 	writel(val, priv->base + divider->reg);
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| 
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| 	return 0;
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| }
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| 
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| static ulong npcm_clk_get_fout(struct clk *clk)
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| {
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| 	ulong parent_rate;
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| 	u32 div;
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| 
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| 	parent_rate = npcm_clk_get_fin(clk);
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| 	if (!parent_rate)
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| 		return -EINVAL;
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| 
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| 	div = npcm_clk_get_div(clk);
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| 	if (!div)
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| 		return -EINVAL;
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| 
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| 	debug("fout of clk%lu = (%lu / %u)\n", clk->id, parent_rate, div);
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| 	return (parent_rate / div);
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| }
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| 
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| static ulong npcm_clk_get_pll_fout(struct clk *clk)
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| {
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| 	struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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| 	struct npcm_clk_pll *pll;
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| 	struct clk parent;
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| 	ulong parent_rate;
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| 	ulong fbdv, indv, otdv1, otdv2;
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| 	u32 val;
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| 	u64 ret;
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| 
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| 	pll = npcm_clk_pll_get(priv->clk_data, clk->id);
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| 	if (!pll)
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| 		return -ENODEV;
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| 
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| 	parent.id = pll->parent_id;
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| 	ret = clk_request(clk->dev, &parent);
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| 	if (ret)
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| 		return ret;
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| 
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| 	parent_rate = clk_get_rate(&parent);
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| 
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| 	val = readl(priv->base + pll->reg);
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| 	indv = FIELD_GET(PLLCON_INDV, val);
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| 	fbdv = FIELD_GET(PLLCON_FBDV, val);
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| 	otdv1 = FIELD_GET(PLLCON_OTDV1, val);
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| 	otdv2 = FIELD_GET(PLLCON_OTDV2, val);
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| 
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| 	ret = (u64)parent_rate * fbdv;
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| 	do_div(ret, indv * otdv1 * otdv2);
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| 	if (pll->flags & POST_DIV2)
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| 		do_div(ret, 2);
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| 
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| 	debug("fout of pll(id %lu) = %llu\n", clk->id, ret);
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| 	return ret;
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| }
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| 
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| static ulong npcm_clk_get_rate(struct clk *clk)
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| {
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| 	struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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| 	struct npcm_clk_data *clk_data = priv->clk_data;
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| 	struct clk refclk;
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| 	int ret;
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| 
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| 	debug("%s: id %lu\n", __func__, clk->id);
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| 	if (clk->id == clk_data->refclk_id) {
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| 		ret = clk_get_by_name(clk->dev, "refclk", &refclk);
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| 		if (!ret)
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| 			return clk_get_rate(&refclk);
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| 		else
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| 			return ret;
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| 	}
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| 
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| 	if (clk->id >= clk_data->pll0_id &&
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| 	    clk->id < clk_data->pll0_id + clk_data->num_plls)
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| 		return npcm_clk_get_pll_fout(clk);
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| 	else
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| 		return npcm_clk_get_fout(clk);
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| }
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| 
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| static ulong npcm_clk_set_rate(struct clk *clk, ulong rate)
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| {
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| 	ulong parent_rate;
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| 	u32 div;
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| 	int ret;
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| 
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| 	debug("%s: id %lu, rate %lu\n", __func__, clk->id, rate);
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| 	parent_rate = npcm_clk_get_fin(clk);
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| 	if (!parent_rate)
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| 		return -EINVAL;
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| 
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| 	div = DIV_ROUND_UP(parent_rate, rate);
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| 	ret = npcm_clk_set_div(clk, div);
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| 	if (ret)
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| 		return ret;
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| 
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| 	debug("%s: rate %lu, new rate %lu\n", __func__, rate, npcm_clk_get_rate(clk));
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| 	return npcm_clk_get_rate(clk);
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| }
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| 
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| static int npcm_clk_set_parent(struct clk *clk, struct clk *parent)
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| {
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| 	struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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| 	struct npcm_clk_select *selector;
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| 	int clksel;
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| 	u32 val;
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| 
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| 	debug("%s: id %lu, parent %lu\n", __func__, clk->id, parent->id);
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| 	selector = npcm_clk_selector_get(priv->clk_data, clk->id);
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| 	if (!selector)
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| 		return -EINVAL;
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| 
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| 	clksel = clkid_to_clksel(selector, parent->id);
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| 	if (clksel < 0)
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| 		return -EINVAL;
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| 
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| 	val = readl(priv->base + selector->reg);
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| 	val &= ~selector->mask;
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| 	val |= clksel << (ffs(selector->mask) - 1);
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| 	writel(val, priv->base + selector->reg);
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| 
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| 	return 0;
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| }
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| 
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| static int npcm_clk_request(struct clk *clk)
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| {
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| 	struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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| 
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| 	if (clk->id >= priv->num_clks)
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| 		return -EINVAL;
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| 
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| 	return 0;
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| }
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| 
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| const struct clk_ops npcm_clk_ops = {
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| 	.get_rate = npcm_clk_get_rate,
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| 	.set_rate = npcm_clk_set_rate,
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| 	.set_parent = npcm_clk_set_parent,
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| 	.request = npcm_clk_request,
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| };
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