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5614e71b49
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
355 lines
7.9 KiB
C
355 lines
7.9 KiB
C
/*
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* Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <ioports.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include "bcsr.h"
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* GETH1 */
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{4, 10, 1, 0, 2}, /* TxD0 */
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{4, 9, 1, 0, 2}, /* TxD1 */
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{4, 8, 1, 0, 2}, /* TxD2 */
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{4, 7, 1, 0, 2}, /* TxD3 */
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{4, 23, 1, 0, 2}, /* TxD4 */
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{4, 22, 1, 0, 2}, /* TxD5 */
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{4, 21, 1, 0, 2}, /* TxD6 */
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{4, 20, 1, 0, 2}, /* TxD7 */
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{4, 15, 2, 0, 2}, /* RxD0 */
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{4, 14, 2, 0, 2}, /* RxD1 */
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{4, 13, 2, 0, 2}, /* RxD2 */
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{4, 12, 2, 0, 2}, /* RxD3 */
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{4, 29, 2, 0, 2}, /* RxD4 */
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{4, 28, 2, 0, 2}, /* RxD5 */
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{4, 27, 2, 0, 2}, /* RxD6 */
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{4, 26, 2, 0, 2}, /* RxD7 */
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{4, 11, 1, 0, 2}, /* TX_EN */
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{4, 24, 1, 0, 2}, /* TX_ER */
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{4, 16, 2, 0, 2}, /* RX_DV */
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{4, 30, 2, 0, 2}, /* RX_ER */
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{4, 17, 2, 0, 2}, /* RX_CLK */
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{4, 19, 1, 0, 2}, /* GTX_CLK */
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{1, 31, 2, 0, 3}, /* GTX125 */
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/* GETH2 */
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{5, 10, 1, 0, 2}, /* TxD0 */
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{5, 9, 1, 0, 2}, /* TxD1 */
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{5, 8, 1, 0, 2}, /* TxD2 */
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{5, 7, 1, 0, 2}, /* TxD3 */
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{5, 23, 1, 0, 2}, /* TxD4 */
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{5, 22, 1, 0, 2}, /* TxD5 */
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{5, 21, 1, 0, 2}, /* TxD6 */
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{5, 20, 1, 0, 2}, /* TxD7 */
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{5, 15, 2, 0, 2}, /* RxD0 */
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{5, 14, 2, 0, 2}, /* RxD1 */
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{5, 13, 2, 0, 2}, /* RxD2 */
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{5, 12, 2, 0, 2}, /* RxD3 */
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{5, 29, 2, 0, 2}, /* RxD4 */
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{5, 28, 2, 0, 2}, /* RxD5 */
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{5, 27, 2, 0, 3}, /* RxD6 */
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{5, 26, 2, 0, 2}, /* RxD7 */
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{5, 11, 1, 0, 2}, /* TX_EN */
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{5, 24, 1, 0, 2}, /* TX_ER */
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{5, 16, 2, 0, 2}, /* RX_DV */
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{5, 30, 2, 0, 2}, /* RX_ER */
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{5, 17, 2, 0, 2}, /* RX_CLK */
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{5, 19, 1, 0, 2}, /* GTX_CLK */
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{1, 31, 2, 0, 3}, /* GTX125 */
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{4, 6, 3, 0, 2}, /* MDIO */
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{4, 5, 1, 0, 2}, /* MDC */
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/* UART1 */
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{2, 0, 1, 0, 2}, /* UART_SOUT1 */
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{2, 1, 1, 0, 2}, /* UART_RTS1 */
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{2, 2, 2, 0, 2}, /* UART_CTS1 */
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{2, 3, 2, 0, 2}, /* UART_SIN1 */
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
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};
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void local_bus_init(void);
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int board_early_init_f (void)
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{
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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enable_8568mds_duart();
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enable_8568mds_flash_write();
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#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
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reset_8568mds_uccs();
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#endif
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#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
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enable_8568mds_qe_mdio();
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#endif
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#ifdef CONFIG_SYS_I2C2_OFFSET
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/* Enable I2C2_SCL and I2C2_SDA */
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volatile struct par_io *port_c;
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port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
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port_c->cpdir2 |= 0x0f000000;
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port_c->cppar2 &= ~0x0f000000;
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port_c->cppar2 |= 0x0a000000;
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#endif
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return 0;
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}
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int checkboard (void)
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{
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printf ("Board: 8568 MDS\n");
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return 0;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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uint clkdiv;
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
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gur->lbiuiplldcr1 = 0x00078080;
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if (clkdiv == 16) {
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gur->lbiuiplldcr0 = 0x7c0f1bf0;
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} else if (clkdiv == 8) {
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gur->lbiuiplldcr0 = 0x6c0f1bf0;
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} else if (clkdiv == 4) {
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gur->lbiuiplldcr0 = 0x5c0f1bf0;
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}
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lbc->lcrr |= 0x00030000;
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asm("sync;isync;msync");
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}
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void lbc_sdram_init(void)
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{
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#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
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uint idx;
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
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uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
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uint lsdmr_common;
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puts("LBC SDRAM: ");
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print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
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"\n ");
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/*
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* Setup SDRAM Base and Option Registers
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*/
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set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
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set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
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asm("msync");
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lbc->lbcr = CONFIG_SYS_LBC_LBCR;
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asm("msync");
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lbc->lsrt = CONFIG_SYS_LBC_LSRT;
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lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
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asm("msync");
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/*
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* MPC8568 uses "new" 15-16 style addressing.
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*/
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lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
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lsdmr_common |= LSDMR_BSMA1516;
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/*
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* Issue PRECHARGE ALL command.
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*/
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lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue 8 AUTO REFRESH commands.
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*/
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for (idx = 0; idx < 8; idx++) {
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lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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}
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/*
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* Issue 8 MODE-set command.
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*/
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lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue NORMAL OP command.
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*/
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lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(200); /* Overkill. Must wait > 200 bus cycles */
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#endif /* enable SDRAM init */
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}
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#if defined(CONFIG_PCI)
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_mpc8568mds_config_table[] = {
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{
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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pci_cfgfunc_config_device,
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{PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
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},
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{}
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};
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#endif
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static struct pci_controller pci1_hose;
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#endif /* CONFIG_PCI */
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/*
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* pib_init() -- Initialize the PCA9555 IO expander on the PIB board
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*/
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void
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pib_init(void)
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{
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u8 val8, orig_i2c_bus;
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/*
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* Assign PIB PMC2/3 to PCI bus
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*/
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/*switch temporarily to I2C bus #2 */
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orig_i2c_bus = i2c_get_bus_num();
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i2c_set_bus_num(1);
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val8 = 0x00;
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i2c_write(0x23, 0x6, 1, &val8, 1);
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i2c_write(0x23, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x23, 0x2, 1, &val8, 1);
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i2c_write(0x23, 0x3, 1, &val8, 1);
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val8 = 0x00;
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i2c_write(0x26, 0x6, 1, &val8, 1);
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val8 = 0x34;
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i2c_write(0x26, 0x7, 1, &val8, 1);
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val8 = 0xf9;
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i2c_write(0x26, 0x2, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x26, 0x3, 1, &val8, 1);
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val8 = 0x00;
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i2c_write(0x27, 0x6, 1, &val8, 1);
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i2c_write(0x27, 0x7, 1, &val8, 1);
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val8 = 0xff;
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i2c_write(0x27, 0x2, 1, &val8, 1);
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val8 = 0xef;
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i2c_write(0x27, 0x3, 1, &val8, 1);
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asm("eieio");
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i2c_set_bus_num(orig_i2c_bus);
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}
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int first_free_busno = 0;
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#ifdef CONFIG_PCI1
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struct fsl_pci_info pci_info;
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u32 devdisr, pordevsr, io_sel;
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u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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porpllsr = in_be32(&gur->porpllsr);
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io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
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pci_speed = 66666000;
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pci_32 = 1;
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pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info, 1);
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set_next_law(pci_info.mem_phys,
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law_size_bits(pci_info.mem_size), pci_info.law);
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set_next_law(pci_info.io_phys,
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law_size_bits(pci_info.io_size), pci_info.law);
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pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
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printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter",
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pci_info.regs);
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#ifndef CONFIG_PCI_PNP
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pci1_hose.config_table = pci_mpc8568mds_config_table;
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#endif
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first_free_busno = fsl_pci_init_port(&pci_info,
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&pci1_hose, first_free_busno);
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} else {
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printf("PCI: disabled\n");
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}
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puts("\n");
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#else
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setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
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#endif
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fsl_pcie_init_board(first_free_busno);
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}
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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FT_FSL_PCI_SETUP;
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}
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#endif
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