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3b4ee40f20
This patch triggers warm reset to recover the MPFE NoC from corruption due to high frequency transient clock output from HPS EMIF IOPLL at VCO startup after peripheral RBF is programmed. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
46 lines
1.5 KiB
C
46 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
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*/
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#ifndef _SYSTEM_MANAGER_ARRIA10_H_
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#define _SYSTEM_MANAGER_ARRIA10_H_
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#define SYSMGR_A10_WDDBG 0x08
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#define SYSMGR_A10_BOOTINFO 0x0c
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#define SYSMGR_A10_DMA 0x20
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#define SYSMGR_A10_DMA_PERIPH 0x24
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#define SYSMGR_A10_SDMMC 0x28
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#define SYSMGR_A10_SDMMC_L3MASTER 0x2c
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#define SYSMGR_A10_EMAC_GLOBAL 0x40
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#define SYSMGR_A10_EMAC0 0x44
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#define SYSMGR_A10_EMAC1 0x48
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#define SYSMGR_A10_EMAC2 0x4c
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#define SYSMGR_A10_FPGAINTF_EN_GLOBAL 0x60
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#define SYSMGR_A10_FPGAINTF_EN0 0x64
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#define SYSMGR_A10_FPGAINTF_EN1 0x68
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#define SYSMGR_A10_FPGAINTF_EN2 0x6c
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#define SYSMGR_A10_FPGAINTF_EN3 0x70
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#define SYSMGR_A10_ECC_INTMASK_VAL 0x90
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#define SYSMGR_A10_ECC_INTMASK_SET 0x94
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#define SYSMGR_A10_ECC_INTMASK_CLR 0x98
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#define SYSMGR_A10_NOC_TIMEOUT 0xc0
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#define SYSMGR_A10_NOC_IDLEREQ_SET 0xc4
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#define SYSMGR_A10_NOC_IDLEREQ_CLR 0xc8
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#define SYSMGR_A10_NOC_IDLEREQ_VAL 0xcc
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#define SYSMGR_A10_NOC_IDLEACK 0xd0
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#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
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#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
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#define SYSMGR_A10_ROMCODE_CTRL 0x204
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#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C
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#define SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND 0x208
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#define SYSMGR_A10_ISW_HANDOFF_BASE 0x230
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#define SYSMGR_A10_ISW_HANDOFF_7 0x1c
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#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
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#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
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#define SYSMGR_BOOTINFO_BSEL_SHIFT 12
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#endif /* _SYSTEM_MANAGER_ARRIA10_H_ */
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