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36756308a2
Commit 7400d34ba992 ("riscv: semihosting: replace inline assembly with
assembly file") reduced the alignment of function smh_trap().
As described in the "RISC-V Semihosting" specification [1] the ssli,
ebreak, and srai statements must all reside in the same memory page.
[1] RISC-V Semihosting, Version 0.4, 12th June 2024
https://github.com/riscv-non-isa/riscv-semihosting
Fixes: 7400d34ba992 ("riscv: semihosting: replace inline assembly with assembly file")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
23 lines
514 B
ArmAsm
23 lines
514 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*/
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#include <asm/asm.h>
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#include <linux/linkage.h>
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.pushsection .text.smh_trap, "ax"
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ENTRY(smh_trap)
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.align 4 /* keep slli, ebreak, srai in same page */
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.option push
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.option norvc /* semihosting sequence must be 32-bit wide */
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slli zero, zero, 0x1f /* Entry NOP to identify semihosting */
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ebreak
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srai zero, zero, 7 /* NOP encoding of semihosting call number */
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.option pop
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ret
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ENDPROC(smh_trap)
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.popsection
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