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03de305ec4
As part of bringing the master branch back in to next, we need to allow for all of these changes to exist here. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com>
126 lines
2.4 KiB
C
126 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012
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* Atmel Semiconductor <www.atmel.com>
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* Written-by: Bo Shen <voice.shen@atmel.com>
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*/
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#include <clk.h>
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#include <dm.h>
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#include <log.h>
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#include <malloc.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include "ehci.h"
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#if !CONFIG_IS_ENABLED(DM_USB)
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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/* Enable UTMI PLL */
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if (at91_upll_clk_enable())
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return -1;
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/* Enable USB Host clock */
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at91_periph_clk_enable(ATMEL_ID_UHPHS);
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*hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;
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*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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/* Disable USB Host Clock */
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at91_periph_clk_disable(ATMEL_ID_UHPHS);
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/* Disable UTMI PLL */
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if (at91_upll_clk_disable())
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return -1;
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return 0;
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}
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#else
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struct ehci_atmel_priv {
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struct ehci_ctrl ehci;
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};
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static int ehci_atmel_enable_clk(struct udevice *dev)
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{
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struct clk clk;
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int ret;
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ret = clk_get_by_index(dev, 0, &clk);
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if (ret)
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return ret;
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ret = clk_enable(&clk);
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if (ret)
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return ret;
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ret = clk_get_by_index(dev, 1, &clk);
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if (ret)
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return -EINVAL;
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return clk_enable(&clk);
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}
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static int ehci_atmel_probe(struct udevice *dev)
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{
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struct ehci_hccr *hccr;
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struct ehci_hcor *hcor;
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fdt_addr_t hcd_base;
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int ret;
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ret = ehci_atmel_enable_clk(dev);
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if (ret) {
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debug("Failed to enable USB Host clock\n");
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return ret;
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}
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/*
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* Get the base address for EHCI controller from the device node
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*/
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hcd_base = dev_read_addr(dev);
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if (hcd_base == FDT_ADDR_T_NONE) {
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debug("Can't get the EHCI register base address\n");
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return -ENXIO;
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}
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hccr = (struct ehci_hccr *)hcd_base;
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hcor = (struct ehci_hcor *)
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((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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debug("echi-atmel: init hccr %x and hcor %x hc_length %d\n",
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(u32)hccr, (u32)hcor,
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(u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
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return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
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}
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static const struct udevice_id ehci_usb_ids[] = {
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{ .compatible = "atmel,at91sam9g45-ehci", },
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{ }
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};
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U_BOOT_DRIVER(ehci_atmel) = {
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.name = "ehci_atmel",
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.id = UCLASS_USB,
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.of_match = ehci_usb_ids,
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.probe = ehci_atmel_probe,
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.remove = ehci_deregister,
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.ops = &ehci_usb_ops,
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.plat_auto = sizeof(struct usb_plat),
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.priv_auto = sizeof(struct ehci_atmel_priv),
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.flags = DM_FLAG_ALLOC_PRIV_DMA,
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};
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#endif
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