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05b60ac549
We want to be able to include some other system headers in phy.h but that requires us to have included common.h in the top-level first. Also, common.h includes config.h as the first thing it does, so don't include it directly. Series-to: u-boot Series-cc: Grygorii Strashko <grygorii.strashko@ti.com> Seried-cc: ti Series-process-log: sort, uniq Cover-letter: Prepare for net: phy: prevent uclass_eth device "node" field overwriting Prepare for [1] so that it doesn't break the build for a bunch of boards. There are a number of reasons this series broke the build but none of them depend on changes in the series, so fix up those situations ahead of applying that series. [1] https://patchwork.ozlabs.org/cover/940104/ END Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
167 lines
3.3 KiB
C
167 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* National Semiconductor PHY drivers
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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*/
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#include <common.h>
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#include <phy.h>
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/* NatSemi DP83630 */
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#define DP83630_PHY_PAGESEL_REG 0x13
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#define DP83630_PHY_PTP_COC_REG 0x14
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#define DP83630_PHY_PTP_CLKOUT_EN (1<<15)
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#define DP83630_PHY_RBR_REG 0x17
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static int dp83630_config(struct phy_device *phydev)
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{
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int ptp_coc_reg;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6);
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ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE,
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DP83630_PHY_PTP_COC_REG);
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ptp_coc_reg &= ~DP83630_PHY_PTP_CLKOUT_EN;
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phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG,
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ptp_coc_reg);
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phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0);
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genphy_config_aneg(phydev);
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return 0;
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}
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static struct phy_driver DP83630_driver = {
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.name = "NatSemi DP83630",
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.uid = 0x20005ce1,
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.mask = 0xfffffff0,
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.features = PHY_BASIC_FEATURES,
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.config = &dp83630_config,
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.startup = &genphy_startup,
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.shutdown = &genphy_shutdown,
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};
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/* DP83865 Link and Auto-Neg Status Register */
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#define MIIM_DP83865_LANR 0x11
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#define MIIM_DP83865_SPD_MASK 0x0018
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#define MIIM_DP83865_SPD_1000 0x0010
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#define MIIM_DP83865_SPD_100 0x0008
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#define MIIM_DP83865_DPX_FULL 0x0002
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/* NatSemi DP83865 */
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static int dp838xx_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
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genphy_config_aneg(phydev);
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return 0;
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}
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static int dp83865_parse_status(struct phy_device *phydev)
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{
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int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DP83865_LANR);
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switch (mii_reg & MIIM_DP83865_SPD_MASK) {
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case MIIM_DP83865_SPD_1000:
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phydev->speed = SPEED_1000;
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break;
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case MIIM_DP83865_SPD_100:
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phydev->speed = SPEED_100;
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break;
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default:
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phydev->speed = SPEED_10;
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break;
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}
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if (mii_reg & MIIM_DP83865_DPX_FULL)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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return 0;
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}
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static int dp83865_startup(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return dp83865_parse_status(phydev);
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}
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static struct phy_driver DP83865_driver = {
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.name = "NatSemi DP83865",
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.uid = 0x20005c70,
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.mask = 0xfffffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &dp838xx_config,
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.startup = &dp83865_startup,
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.shutdown = &genphy_shutdown,
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};
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/* NatSemi DP83848 */
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static int dp83848_parse_status(struct phy_device *phydev)
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{
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int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
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if(mii_reg & (BMSR_100FULL | BMSR_100HALF)) {
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phydev->speed = SPEED_100;
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} else {
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phydev->speed = SPEED_10;
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}
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if (mii_reg & (BMSR_10FULL | BMSR_100FULL)) {
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phydev->duplex = DUPLEX_FULL;
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} else {
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phydev->duplex = DUPLEX_HALF;
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}
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return 0;
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}
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static int dp83848_startup(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return dp83848_parse_status(phydev);
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}
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static struct phy_driver DP83848_driver = {
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.name = "NatSemi DP83848",
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.uid = 0x20005c90,
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.mask = 0x2000ff90,
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.features = PHY_BASIC_FEATURES,
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.config = &dp838xx_config,
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.startup = &dp83848_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_natsemi_init(void)
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{
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phy_register(&DP83630_driver);
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phy_register(&DP83865_driver);
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phy_register(&DP83848_driver);
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return 0;
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}
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