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Common practice on Tegra 2 boards is to use the pllp_out4 FO to generate the ULPI reference clock. For this to work we have to override the default hardware generated output divider. This function adds a clean way to do so. Signed-off-by: Lucas Stach <dev@lynxeye.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
155 lines
5.3 KiB
C
155 lines
5.3 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _CLK_RST_H_
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#define _CLK_RST_H_
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/* PLL registers - there are several PLLs in the clock controller */
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struct clk_pll {
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uint pll_base; /* the control register */
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uint pll_out[2]; /* output control */
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uint pll_misc; /* other misc things */
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};
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/* PLL registers - there are several PLLs in the clock controller */
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struct clk_pll_simple {
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uint pll_base; /* the control register */
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uint pll_misc; /* other misc things */
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};
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/*
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* Most PLLs use the clk_pll structure, but some have a simpler two-member
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* structure for which we use clk_pll_simple. The reason for this non-
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* othogonal setup is not stated.
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*/
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enum {
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TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */
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TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */
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TEGRA_CLK_REGS = 3, /* Number of clock enable registers */
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TEGRA_CLK_SOURCES = 64, /* Number of peripheral clock sources */
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};
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/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
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struct clk_rst_ctlr {
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uint crc_rst_src; /* _RST_SOURCE_0,0x00 */
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uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
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uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
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uint crc_reserved0; /* reserved_0, 0x1C */
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uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */
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uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
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uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
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uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
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uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
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uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
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uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */
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uint crc_reserved1; /* reserved_1, 0x3C */
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uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */
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uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
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uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
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uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */
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uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */
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uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */
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uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
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uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */
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uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */
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struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */
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/* PLLs from 0xe0 to 0xf4 */
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struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
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uint crc_reserved10; /* _reserved_10, 0xF8 */
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uint crc_reserved11; /* _reserved_11, 0xFC */
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uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
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uint crc_reserved20[80]; /* 0x200-33C */
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uint crc_cpu_cmplx_set; /* _CPU_CMPLX_SET_0, 0x340 */
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uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
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};
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/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
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#define CPU1_CLK_STP_SHIFT 9
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#define CPU0_CLK_STP_SHIFT 8
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#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
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/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
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#define PLL_BYPASS_SHIFT 31
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#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT)
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#define PLL_ENABLE_SHIFT 30
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#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT)
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#define PLL_BASE_OVRRIDE_MASK (1U << 28)
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#define PLL_DIVP_SHIFT 20
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#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
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#define PLL_DIVN_SHIFT 8
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#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT)
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#define PLL_DIVM_SHIFT 0
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#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT)
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/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
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#define PLL_OUT_RSTN (1 << 0)
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#define PLL_OUT_CLKEN (1 << 1)
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#define PLL_OUT_OVRRIDE (1 << 2)
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#define PLL_OUT_RATIO_SHIFT 8
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#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
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/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
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#define PLL_CPCON_SHIFT 8
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#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
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#define PLL_LFCON_SHIFT 4
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#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT)
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#define PLLU_VCO_FREQ_SHIFT 20
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#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
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/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
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#define OSC_FREQ_SHIFT 30
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#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
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#define OSC_XOBP_SHIFT 1
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#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
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/*
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* CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits
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* but can be 16. We could use knowledge we have to restrict the mask in
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* the 8-bit cases (the divider_bits value returned by
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* get_periph_clock_source()) but it does not seem worth it since the code
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* already checks the ranges of values it is writing, in clk_get_divider().
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*/
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#define OUT_CLK_DIVISOR_SHIFT 0
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#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT)
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#define OUT_CLK_SOURCE_SHIFT 30
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#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT)
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#define OUT_CLK_SOURCE4_SHIFT 28
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#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT)
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#endif /* CLK_RST_H */
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