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9e75875849
Add support for Freescale T4240 SoC. Feature of T4240 are
(incomplete list):
12 dual-threaded e6500 cores built on Power Architecture® technology
Arranged as clusters of four cores sharing a 2 MB L2 cache.
Up to 1.8 GHz at 1.0 V with 64-bit ISA support (Power Architecture
v2.06-compliant)
Three levels of instruction: user, supervisor, and hypervisor
1.5 MB CoreNet Platform Cache (CPC)
Hierarchical interconnect fabric
CoreNet fabric supporting coherent and non-coherent transactions with
prioritization and bandwidth allocation amongst CoreNet end-points
1.6 Tbps coherent read bandwidth
Queue Manager (QMan) fabric supporting packet-level queue management and
quality of service scheduling
Three 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
support
Memory prefetch engine (PMan)
Data Path Acceleration Architecture (DPAA) incorporating acceleration for
the following functions:
Packet parsing, classification, and distribution (Frame Manager 1.1)
Queue management for scheduling, packet sequencing, and congestion
management (Queue Manager 1.1)
Hardware buffer management for buffer allocation and de-allocation
(BMan 1.1)
Cryptography acceleration (SEC 5.0) at up to 40 Gbps
RegEx Pattern Matching Acceleration (PME 2.1) at up to 10 Gbps
Decompression/Compression Acceleration (DCE 1.0) at up to 20 Gbps
DPAA chip-to-chip interconnect via RapidIO Message Manager (RMAN 1.0)
32 SerDes lanes at up to 10.3125 GHz
Ethernet interfaces
Up to four 10 Gbps Ethernet MACs
Up to sixteen 1 Gbps Ethernet MACs
Maximum configuration of 4 x 10 GE + 8 x 1 GE
High-speed peripheral interfaces
Four PCI Express 2.0/3.0 controllers
Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz with
Type 11 messaging and Type 9 data streaming support
Interlaken look-aside interface for serial TCAM connection
Additional peripheral interfaces
Two serial ATA (SATA 2.0) controllers
Two high-speed USB 2.0 controllers with integrated PHY
Enhanced secure digital host controller (SD/MMC/eMMC)
Enhanced serial peripheral interface (eSPI)
Four I2C controllers
Four 2-pin or two 4-pin UARTs
Integrated Flash controller supporting NAND and NOR flash
Two eight-channel DMA engines
Support for hardware virtualization and partitioning enforcement
QorIQ Platform's Trust Architecture 1.1
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
238 lines
7.7 KiB
C
238 lines
7.7 KiB
C
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "fsl_corenet2_serdes.h"
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struct serdes_config {
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u32 protocol;
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u8 lanes[SRDS_MAX_LANES];
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};
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static struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
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{4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
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{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
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{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
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{38, {NONE, NONE, QSGMII_FM1_B, NONE,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{}
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};
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static struct serdes_config serdes2_cfg_tbl[] = {
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/* SerDes 2 */
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{1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC10, XAUI_FM2_MAC10,
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XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
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{2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
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HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
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{4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
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HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
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{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{38, {NONE, NONE, QSGMII_FM2_B, NONE,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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XFI_FM2_MAC10, XFI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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XFI_FM2_MAC10, XFI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{}
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};
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static struct serdes_config serdes3_cfg_tbl[] = {
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/* SerDes 3 */
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{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
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{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
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{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
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{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
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{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
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{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
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{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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PCIE2, PCIE2, PCIE2, PCIE2}},
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{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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PCIE2, PCIE2, PCIE2, PCIE2}},
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{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{}
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};
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static struct serdes_config serdes4_cfg_tbl[] = {
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/* SerDes 4 */
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{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
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{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
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{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
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{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
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{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA1}},
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{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA1}},
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{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
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{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
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{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
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{}
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};
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static struct serdes_config *serdes_cfg_tbl[] = {
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serdes1_cfg_tbl,
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serdes2_cfg_tbl,
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serdes3_cfg_tbl,
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serdes4_cfg_tbl,
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == cfg)
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return ptr->lanes[lane];
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ptr++;
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}
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return 0;
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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struct serdes_config *ptr;
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if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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ptr = serdes_cfg_tbl[serdes];
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while (ptr->protocol) {
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if (ptr->protocol == prtcl)
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break;
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ptr++;
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}
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if (!ptr->protocol)
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (ptr->lanes[i] != NONE)
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return 1;
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}
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return 0;
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}
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