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c360ceac02
- support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
292 lines
8.0 KiB
C
292 lines
8.0 KiB
C
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include "ddr.h"
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/* Board-specific functions defined in each board's ddr.c */
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extern void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num);
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unsigned int populate_memctl_options(int all_DIMMs_registered,
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memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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unsigned int i;
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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const char *p;
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#endif
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/* Chip select options. */
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/* Pick chip-select local options. */
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for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
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/* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
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/* only for single CS? */
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popts->cs_local_opts[i].odt_rd_cfg = 0;
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popts->cs_local_opts[i].odt_wr_cfg = 1;
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popts->cs_local_opts[i].auto_precharge = 0;
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}
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/* Pick interleaving mode. */
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/*
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* 0 = no interleaving
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* 1 = interleaving between 2 controllers
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*/
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popts->memctl_interleaving = 0;
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/*
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* 0 = cacheline
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* 1 = page
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* 2 = (logical) bank
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* 3 = superbank (only if CS interleaving is enabled)
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*/
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popts->memctl_interleaving_mode = 0;
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/*
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* 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
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* 1: page: bit to the left of the column bits selects the memctl
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* 2: bank: bit to the left of the bank bits selects the memctl
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* 3: superbank: bit to the left of the chip select selects the memctl
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*
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* NOTE: ba_intlv (rank interleaving) is independent of memory
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* controller interleaving; it is only within a memory controller.
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* Must use superbank interleaving if rank interleaving is used and
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* memory controller interleaving is enabled.
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*/
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/*
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* 0 = no
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* 0x40 = CS0,CS1
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* 0x20 = CS2,CS3
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* 0x60 = CS0,CS1 + CS2,CS3
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* 0x04 = CS0,CS1,CS2,CS3
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*/
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popts->ba_intlv_ctl = 0;
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/* Memory Organization Parameters */
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popts->registered_dimm_en = all_DIMMs_registered;
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/* Operational Mode Paramters */
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/* Pick ECC modes */
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#ifdef CONFIG_DDR_ECC
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popts->ECC_mode = 1; /* 0 = disabled, 1 = enabled */
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#else
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popts->ECC_mode = 0; /* 0 = disabled, 1 = enabled */
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#endif
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popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
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/*
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* Choose DQS config
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* 0 for DDR1
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* 1 for DDR2
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*/
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#if defined(CONFIG_FSL_DDR1)
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popts->DQS_config = 0;
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#elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
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popts->DQS_config = 1;
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#endif
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/* Choose self-refresh during sleep. */
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popts->self_refresh_in_sleep = 1;
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/* Choose dynamic power management mode. */
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popts->dynamic_power = 0;
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/* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
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popts->data_bus_width = 0;
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/* Choose burst length. */
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#if defined(CONFIG_FSL_DDR3)
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popts->OTF_burst_chop_en = 1; /* on-the-fly burst chop */
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popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
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#else
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popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
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#endif
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/* Choose ddr controller address mirror mode */
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#if defined(CONFIG_FSL_DDR3)
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popts->mirrored_dimm = pdimm[0].mirrored_dimm;
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#endif
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/* Global Timing Parameters. */
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debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
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/* Pick a caslat override. */
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popts->cas_latency_override = 0;
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popts->cas_latency_override_value = 3;
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if (popts->cas_latency_override) {
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debug("using caslat override value = %u\n",
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popts->cas_latency_override_value);
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}
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/* Decide whether to use the computed derated latency */
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popts->use_derated_caslat = 0;
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/* Choose an additive latency. */
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popts->additive_latency_override = 0;
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popts->additive_latency_override_value = 3;
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if (popts->additive_latency_override) {
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debug("using additive latency override value = %u\n",
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popts->additive_latency_override_value);
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}
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/*
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* 2T_EN setting
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*
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* Factors to consider for 2T_EN:
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* - number of DIMMs installed
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* - number of components, number of active ranks
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* - how much time you want to spend playing around
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*/
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popts->twoT_en = 0;
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popts->threeT_en = 0;
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/*
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* BSTTOPRE precharge interval
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*
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* Set this to 0 for global auto precharge
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*
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* FIXME: Should this be configured in picoseconds?
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* Why it should be in ps: better understanding of this
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* relative to actual DRAM timing parameters such as tRAS.
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* e.g. tRAS(min) = 40 ns
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*/
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popts->bstopre = 0x100;
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/* Minimum CKE pulse width -- tCKE(MIN) */
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popts->tCKE_clock_pulse_width_ps
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= mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
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/*
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* Window for four activates -- tFAW
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*
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* FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
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* FIXME: varies depending upon number of column addresses or data
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* FIXME: width, was considering looking at pdimm->primary_sdram_width
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*/
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#if defined(CONFIG_FSL_DDR1)
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popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
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#elif defined(CONFIG_FSL_DDR2)
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/*
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* x4/x8; some datasheets have 35000
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* x16 wide columns only? Use 50000?
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*/
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popts->tFAW_window_four_activates_ps = 37500;
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#elif defined(CONFIG_FSL_DDR3)
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popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
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#endif
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popts->zq_en = 0;
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popts->wrlvl_en = 0;
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#if defined(CONFIG_FSL_DDR3)
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/*
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* due to ddr3 dimm is fly-by topology
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* we suggest to enable write leveling to
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* meet the tQDSS under different loading.
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*/
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popts->wrlvl_en = 1;
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#endif
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/*
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* Check interleaving configuration from environment.
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* Please refer to doc/README.fsl-ddr for the detail.
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*
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* If memory controller interleaving is enabled, then the data
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* bus widths must be programmed identically for the 2 memory
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* controllers.
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*
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* XXX: Attempt to set both controllers to the same chip select
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* interleaving mode. It will do a best effort to get the
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* requested ranks interleaved together such that the result
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* should be a subset of the requested configuration.
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*/
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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if ((p = getenv("memctl_intlv_ctl")) != NULL) {
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if (pdimm[0].n_ranks == 0) {
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printf("There is no rank on CS0. Because only rank on "
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"CS0 and ranks chip-select interleaved with CS0"
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" are controller interleaved, force non memory "
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"controller interleaving\n");
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popts->memctl_interleaving = 0;
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} else {
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popts->memctl_interleaving = 1;
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if (strcmp(p, "cacheline") == 0)
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popts->memctl_interleaving_mode =
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FSL_DDR_CACHE_LINE_INTERLEAVING;
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else if (strcmp(p, "page") == 0)
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popts->memctl_interleaving_mode =
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FSL_DDR_PAGE_INTERLEAVING;
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else if (strcmp(p, "bank") == 0)
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popts->memctl_interleaving_mode =
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FSL_DDR_BANK_INTERLEAVING;
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else if (strcmp(p, "superbank") == 0)
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popts->memctl_interleaving_mode =
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FSL_DDR_SUPERBANK_INTERLEAVING;
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else
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popts->memctl_interleaving_mode =
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simple_strtoul(p, NULL, 0);
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}
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}
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if( (p = getenv("ba_intlv_ctl")) != NULL) {
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if (strcmp(p, "cs0_cs1") == 0)
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popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
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else if (strcmp(p, "cs2_cs3") == 0)
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popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
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else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
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popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
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else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
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popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
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else
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popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
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switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
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case FSL_DDR_CS0_CS1_CS2_CS3:
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case FSL_DDR_CS0_CS1:
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if (pdimm[0].n_ranks != 2) {
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popts->ba_intlv_ctl = 0;
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printf("Not enough bank(chip-select) for "
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"CS0+CS1, force non-interleaving!\n");
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}
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break;
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case FSL_DDR_CS2_CS3:
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if (pdimm[1].n_ranks !=2){
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popts->ba_intlv_ctl = 0;
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printf("Not enough bank(CS) for CS2+CS3, "
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"force non-interleaving!\n");
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}
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break;
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case FSL_DDR_CS0_CS1_AND_CS2_CS3:
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if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
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popts->ba_intlv_ctl = 0;
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printf("Not enough bank(CS) for CS0+CS1 or "
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"CS2+CS3, force non-interleaving!\n");
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}
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break;
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default:
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popts->ba_intlv_ctl = 0;
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break;
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}
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}
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#endif
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fsl_ddr_board_options(popts, pdimm, ctrl_num);
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return 0;
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}
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