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Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL iMX6ULL SoM. CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: Variscite DART-6UL Evaluation Kit Board: Variscite DART-6UL Evaluation Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2c - MMC/SD - eMMC - USB host - UART 1 Note: LCDIF porting needs DM_VIDEO https://lists.denx.de/pipermail/u-boot/2019-April/365506.html Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>
40 lines
638 B
Plaintext
40 lines
638 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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*/
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/dts-v1/;
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#include "imx6ull.dtsi"
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#include "imx6ull-dart-6ul.dtsi"
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/ {
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model = "Variscite DART-6UL Evaluation Kit";
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compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
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};
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&usdhc2 {
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb_otg1_id>;
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dr_mode = "otg";
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srp-disable;
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hnp-disable;
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adp-disable;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_usb_otg1_id: usbotg1idgrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
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>;
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};
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};
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