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Based on the MCU R5 efuse settings, R5F cores in MCU domain either work in split mode or in lock step mode. If efuse settings are in lockstep mode: ROM release R5 cores and SPL continues to run on the R5 core is lockstep mode. If efuse settings are in split mode: ROM releases both the R5 cores simultaneously and allow SPL to run on both the cores. In this case it is bootloader's responsibility to detect core 1 and park it. Else both the core will be running bootloader independently which might result in an unexpected behaviour. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
21 lines
351 B
ArmAsm
21 lines
351 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <linux/linkage.h>
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ENTRY(lowlevel_init)
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mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
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and r0, #0xff
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cmp r0, #0x0
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bne park_cpu
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bx lr
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park_cpu:
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wfi
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b park_cpu
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ENDPROC(lowlevel_init)
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