mirror of
https://github.com/smaeul/u-boot.git
synced 2025-10-31 12:08:19 +00:00
f86ed75059
Move Stratix10 and Agilex SPL common code to spl_soc64.c. We are in preparation for new n5x device support. No functional change in this patch. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
95 lines
2.1 KiB
C
95 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
|
|
*
|
|
*/
|
|
|
|
#include <hang.h>
|
|
#include <init.h>
|
|
#include <log.h>
|
|
#include <asm/global_data.h>
|
|
#include <asm/io.h>
|
|
#include <asm/u-boot.h>
|
|
#include <asm/utils.h>
|
|
#include <common.h>
|
|
#include <debug_uart.h>
|
|
#include <image.h>
|
|
#include <spl.h>
|
|
#include <asm/arch/clock_manager.h>
|
|
#include <asm/arch/firewall.h>
|
|
#include <asm/arch/mailbox_s10.h>
|
|
#include <asm/arch/misc.h>
|
|
#include <asm/arch/reset_manager.h>
|
|
#include <asm/arch/system_manager.h>
|
|
#include <watchdog.h>
|
|
#include <dm/uclass.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
const struct cm_config *cm_default_cfg = cm_get_default_config();
|
|
int ret;
|
|
|
|
ret = spl_early_init();
|
|
if (ret)
|
|
hang();
|
|
|
|
socfpga_get_managers_addr();
|
|
|
|
/* Ensure watchdog is paused when debugging is happening */
|
|
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
|
|
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
|
|
|
|
#ifdef CONFIG_HW_WATCHDOG
|
|
/* Enable watchdog before initializing the HW */
|
|
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
|
|
socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
|
|
hw_watchdog_init();
|
|
#endif
|
|
|
|
/* ensure all processors are not released prior Linux boot */
|
|
writeq(0, CPU_RELEASE_ADDR);
|
|
|
|
socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
|
|
timer_init();
|
|
|
|
sysmgr_pinmux_init();
|
|
|
|
/* configuring the HPS clocks */
|
|
cm_basic_init(cm_default_cfg);
|
|
|
|
#ifdef CONFIG_DEBUG_UART
|
|
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
|
|
debug_uart_init();
|
|
#endif
|
|
|
|
preloader_console_init();
|
|
print_reset_info();
|
|
cm_print_clock_quick_summary();
|
|
|
|
firewall_setup();
|
|
|
|
/* disable ocram security at CCU for non secure access */
|
|
clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
|
|
CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
|
|
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
|
|
CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
|
|
|
|
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
|
|
struct udevice *dev;
|
|
|
|
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
|
if (ret) {
|
|
debug("DRAM init failed: %d\n", ret);
|
|
hang();
|
|
}
|
|
#endif
|
|
|
|
mbox_init();
|
|
|
|
#ifdef CONFIG_CADENCE_QSPI
|
|
mbox_qspi_open();
|
|
#endif
|
|
}
|